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6.7
SAVING CMOS RAM DATA IN THE SERIAL EEPROM
A serial EEPROM chip on the TP400 provides non-volatile memory storage and also
incorporates a watchdog timer. The non-volatile memory can be used to back-up the
CMOS SRAM, in systems without batteries, or where the battery may go flat. The
serial EEPROM chip used is the Xicor X5043. This chip contains 512 bytes of non-
volatile serial EEPROM. The serial EEPROM is accessed through the Utility Register
in the PC97317 Super I/O chip.
The BIOS includes a feature that checks to see if the contents of the CMOS memory
are valid during the boot sequence. If the CMOS memory does not have valid
contents (since there was no battery back-up, for instance) then the BIOS will check
whether the serial EEPROM contains valid CMOS data. If it does then the data in the
serial EEPROM memory will be copied into the CMOS memory and used.
It is the responsibility of the user to program the serial EEPROM. A utility program is
provided to do this. It is called TP3EE.EXE and is available on the TP400 Utility
Disks. It should be run with the -C parameter, like this:
TP3EE
-C
(Note that the TP3EE program has other uses - see 6.8 and 6.9).
The TP3EE program should be run once the CMOS memory contains valid data -
after running the BIOS Setup program for instance. The contents of the CMOS
registers are then copied into the serial EEPROM. These values will be returned to
the CMOS memory by the BIOS if the CMOS memory contains invalid data during
subsequent boot operations.
When the TP3EE.EXE program is run all of the first 128 locations in the CMOS
SRAM module are copied to the EEPROM. Note the 128 locations are made up of
114 CMOS RAM locations, ten real-time clock time and date registers and four
control registers. All 128 are copied to the serial EEPROM. A checksum is added
then appended to the CMOS data in the serial EEPROM. (There are a further 128
CMOS memory locations that can be accessed in a different bank in the PC97317.
These locations are not copied to the serial EEPROM.)
During the restore process, when the contents of the serial EEPROM are copied back
to the CMOS RAM, all 128 bytes are copied. This restores the time and date, the
control registers and the memory locations containing data.
The BIOS makes use of all of the first 114 CMOS memory locations. There is further
CMOS SRAM available, which can be accessed by setting the bank select bits in the
PC97317 Super I/O chip. This is discussed in the PC97317 data book. Users who
require additional SRAM may use the SRAM in other banks.
Although only the first 130 locations in the serial EEPROM are currently used by the
BIOS to store the CMOS registers, DSP Design strongly recommends that 256
locations in the serial EEPROM up to and including address 0FFh are reserved for
possible future BIOS use. This leaves a further 256 bytes in the serial EEPROM (at
addresses 100h - 1FFh) available for users. Section 6.8 describes a program that can
be used to read and write CMOS EEPROM locations.
Summary of Contents for 104-plus
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Page 136: ...J2 164004 C03 FIGURE J1 TP400ET MECHANICAL DRAWINGS FIGURE J2 TP400ET CIRCUIT DIAGRAM ...
Page 138: ...K2 158004 B00 FIGURE K1 TP300USB MECHANICAL DRAWINGS FIGURE K2 TP300USB CIRCUIT DIAGRAM ...