DSP 104-plus, Reference Manual

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5 HARDWARE RESET OPTIONS
A full set of hardware reset options exist for the TP400. The reset circuit is built
around the X5043 serial EEPROM chip, which provides reset functions as well as
memory. This chip includes a power supply monitor and a watchdog timer. To avoid
glitches on the reset signal, the X5043 will always hold the reset signal asserted for
approximately 200ms. This ensures all circuitry is properly reset, and conforms to the
PC/104 bus specification.
The X5043 resets the CS5530A chip, on-board circuitry and the PC/104 bus. The
CS5530A chip responds to its reset by resetting the Geode GX1 processor and the
PCI bus.
5.1 POWER SUPPLY MONITOR
The X5043 monitors the +5V supply voltage. When the supply drops below about
4.5V the X5043 will assert the TP400 reset signal. Once the power supply returns to
within specification, the reset signal will be released after further 200ms. This circuit
prevents power "brown-out" causing unpredictable behavior.
Users should note that if the voltage drop across the cables that link the power supply
to the TP400 is excessive then the power supply monitor may reset the TP400. This
may also happen if there are noise spikes on the power supply. It is recommended
that all power supply cables be as thick and short as possible to minimize the voltage
drop across them.
5.2 ONBOARD WATCHDOG TIMER
A watchdog timer exists on the X5043. The function of a watchdog timer is to reset a
computer if the software has crashed. The correct operation of the timer relies on
software to access the watchdog timer hardware on a regular basis. If the software
crashes, the watchdog timer will not be "kicked" and so eventually it will time-out and
reset the computer. The watchdog timer function is accessed via the Utility Register.
The Utility Register is a multi-function register that among other things gives access
to the four control signals on the X5043 serial EEPROM. The Utility Register is
described in section 3.18. The watchdog is enabled by writing an enable command to
the X5043 via the Utility Register. Once this has been initiated, an internal clock to
the X5043 starts counting and will continue to count until it times out, until the
watchdog timer is “kicked” by the user’s application software, or until the watchdog
timer is disabled by a disable command sent to the X5043.
The watchdog timer period can be set to approximately 1.4s, 600ms or 200ms, or it
can be disabled, by writing different command words to the serial EEPROM
command register. Once it has been enabled the watchdog timer must be accessed
repeatedly by the user’s software. If the watchdog timer is allowed to time out the
X5043 chip will issue a hardware reset to the TP400 (and to the PC/104 and PC/104
buses).
The watchdog timer is “kicked” by taking its chip select (/CS) pin low then high. The
/CS pin is driven by bit 4 of the Utility Register at I/O address 0E4h. The TP400 Utility