Digilent Cora Z7, Reference Manual, Page: 8 / 23

7/30/2019 Cora Z7 Reference Manual [Reference.Digilentinc]
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(https://reference.digilentinc.com/_detail/zybo/zyng1.png?id=reference%3Aprogrammable-logic%3Acora-z7%3Areference-manual)
Figure 2.1 Zynq APSoC architecture
The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses that tightly couple it to
the PS. The PL also does not contain the same configuration hardware as a typical 7-series FPGA, and it must be configured either directly
by the processor or via the JTAG port.
The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture
(AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54
dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU
only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O
through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the
AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The
programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each
also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections
not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory.
There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough
description, refer to the
Zynq Technical Reference Manual
(http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-
TRM.pdf)
.
Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the Cora Z7
Resource Center
(https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start)
can be imported into EDK and Vivado Designs
to properly configure the PS to work with these peripherals.
MIO 500 (3.3 V) Peripherals
Pin Configuration Mode ENET 0 USB 0 Shield UART 0
0 (N/C)
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