7/30/2019
Cora Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual?_ga=2.21685883.1349070004.1564406803-1961480359.… 15/23
ACT
LD9
Blinking
Transmitting or Receiving
Table 8.1. Ethernet status LEDs.
The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of
these two, GEM 0 can be mapped to the MIO pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII
interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF).
Mapping out the correct pins and configuring the interface is handled by the Cora Z7 Zynq Presets file, available on the Cora Z7 Resource
Center
(https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start)
Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for
management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands,
status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic
configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL
and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The RTL8211E-VL is capable of inserting a 2ns delay on
both the TXC and RXC so that board traces do not need to be made longer.
The PHY is clocked from the same 50 MHz () oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough
to be driven from a single source.
On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory,
displaying a 48-bit globally unique EUI-48/64™ compatible identifier.
For more information on using the Gigabit Ethernet MAC, refer to the
Zynq Technical Reference manual
(http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
The Cora Z7 provides a 50 MHz () clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System
(PS) subsystems. The 50 MHz () input allows the processor to operate at a maximum frequency of 650 MHz () and the DDR3 memory
controller to operate at a maximum of 525 MHz () (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board
File package (Installation Instructions
(https://reference.digilentinc.com/vivado/installing-vivado/start#installing_digilent_board_files)
) can be
imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz () input
clock.
The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, that can
be used to clock custom logic implemented in the Programmable Logic (PL). Additionally, the Cora Z7 provides an external 125 MHz ()
reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS,
which can be useful for simple applications that do not require the processor.
The PL of the Zynq also includes Mixed-Mode Clock Managers (MMCM) and PLLs that can be used to generate clocks with precise
frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz () external reference clock can be used as an input
to the MMCMs and PLLs. Both the Cora Z7-07S and Z7-10 include 2 MMCM's and 2 PLL's. For a full description of the capabilities of the
Zynq PL clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.
Figure 9.1 outlines the clocking scheme used on the Cora Z7. Note that the reference clock output from the Ethernet PHY is used as the
125 MHz () reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that
CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low.
9 Clock Sources