7/30/2019
Cora Z7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/cora-z7/reference-manual?_ga=2.21685883.1349070004.1564406803-1961480359.… 12/23
4. Eject the microSD card from the host computer and insert it into connector J10 on the Cora Z7.
5. Attach a power source to the Cora Z7 and select it using JP3.
6. Place a jumper on JP2, shorting the two pins together.
7. Turn the board on. The board will now boot the image on the microSD card.
When placed in JTAG boot mode, the processor will wait until software is loaded by a host computer using the Xilinx tools. After software
has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK.
It is also possible to directly configure the PL over JTAG, independent of the processor. This can be done using the Vivado Hardware
Server.
The Cora Z7 includes a Micron MT41K256M16HA-125 DDR3L memory component, creating a single rank 16-bit wide interface and a
total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor
Subsystem (PS), as outlined in the Zynq documentation.
The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory
interface speeds up to 533 MHz ()/1066 Mbps are supported.
The Cora Z7 was routed with 40 ohm (+/-10%) trace impedance for single-ended signals, and differential clock and strobes set to 80 ohms
(+/-10%). A feature called DCI (Digitally Controlled Impedance) is used to match the drive strength and termination impedance of the PS
pins to the trace impedance. On the memory side, the DDR3L chip calibrates its on-die termination and drive strength using a 240 ohm
resistor on the ZQ pin.
Due to layout reasons, the two data byte groups (DQ[0-7], DQ[8-15]) were swapped. To the same effect, the data bits inside byte groups
were swapped as well. These changes are transparent to the user. During the whole design process the Xilinx PCB guidelines were followed.
Both the memory chip and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of 0.675V is created with a
simple resistor divider and is available to the Zynq as external reference.
For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to
the board trace delays. For your convenience, the Cora Z7 Vivado board files are available on the Cora Z7 Resource Center
(https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start)
and automatically configure the Zynq Processing System IP core
with the correct parameters.
For best DDR3L performance, DRAM training is enabled for write leveling, read gate, and read data eye options in the PS Configuration
Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays, process variations and thermal drift.
Optimum starting values for the training process are the board delays (propagation delays) for certain memory signals.
Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length
reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design.
For more details on memory controller operation, refer to the Xilinx
Zynq Technical Reference manual
(http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
The Cora Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J12) that lets you use PC applications to
communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in
Windows and newer versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the
drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The
port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller.
The Zynq presets file (available through the Cora Z7 Resource Center
(https://reference.digilentinc.com/reference/programmable-logic/cora-
baud rate, 1 stop bit, no parity, 8-bit character length.
Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED () (LD5) and the receive LED ()
(LD4). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.
The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions behave
entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not
need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two features
3.2 JTAG Boot Mode
4 DDR3L Memory
5 USB UART Bridge (Serial Port)
