Elton User Manual Rev 1.04
Page 12
The USB 3.0 device controller enables the AGX Xavier Series Module to be accessed from an external Host
device. The controller supports USB 2.0 or USB 3.0 with up to 15 IN and 15 OUT Endpoints, which can be
configured to support transfer types of different input devices such as a modem or a storage drive.
Both, the xHCI and USB 3.0 device controllers support USB Link Power Management (LPM) features:
Remote Wakeup
,
Wake On Connect
,
Wake On Disconnect
, and
Wake On Over Current
, in all
power states, including
Deep Sleep
mode.
USB 3.1 ports support both, Gen 1-SuperSpeed and Gen 2-SuperSpeed at 10 Gbps transfer rates. USB 3.1
port 0 and port 3 share one 10 Gbps unit bandwidth, while USB 3.1 is allocated a separate 10 Gbps unit
bandwidth. All USB 3.1 ports support hardware initiated U1 and U2 Link Power Management as well as
software initiated U3 (suspend) Link Power Management.
Universal Flash Storage (UFS) Controller
The Universal Flash Storage controller in the AGX Xavier Series Module integrates the following blocks:
A Universal Flash Storage Host Controller (UFSHC)
A MIPI Unified Protocol (UniPro) Interface Controller
Two MIPI M-PHY (MPHY) High-Speed Serial Interfaces
The UFS blocks can be operated in single (x1) or dual (x2) lane configurations to support operations at high-
speed (HS)-G1, HS-G2, and HS-G3, at both, Rate A and Rate B speeds. MPHY modules drive the physical
link and convert parallel data streams from the high-speed serializer into a high-speed differential or low-
speed Pulse-Width Modulation (PWM)-like transmissions.
The PCIe, USB 3.1, and UFS Transport Protocol Mapping on the AGX Xavier Series Module are specified
in the table below.
Signal/Pin Name
Mapping
UPHY0 (x1 PCIe)
1 to 5 Port PCIe Switch
UPHY1 (USB 3.1)
USB 3.1 Header
UPHY [5:2] (x4 PCIe)
M.2 PCIe
UPHY6 (USB 3.1)
USB 3.1 Header
UPHY7 (x1 PCIe)
I210 Ethernet Controller
UPHY8 (x1 PCIe)
PCIe to PCI Bridges
UPHY10 (x1 PCIe)
UFS Card Socket
NVHS0_ [7:0]
PCIe/104 Bank 2 and 3
A 6-port PCIe Gen 2 switch with x1 lane upstream port to 5nos of x1 downstream ports are utilized for
effective IO expansion functionalities.
The downstream port assignments on the switch are specified in the table below.
Switch
Port
Assignment
PCIe Switch
Port1
PCIe/104 Bank1 Port1
PCIe Switch
Port2
PCIe/104 Bank1 Port2
PCIe Switch
Port3
PCIe/104 Bank1 Port3
PCIe Switch
Port4
PCIe/104 Bank1 Port4
PCIe Switch
Port5
Mini PCIe Card
