Athena III User Manual Rev A.03
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Page
76
20.3.3
Disabling the Counter Gate Command
Disabling the counter gate, as shown below, causes the counter to run continuously.
Counter 0:
Counter 1:
outp(base+15,0x20);
outp(base+15,0xA0);
20.3.4
Clearing a Counter Sequence
Clear a counter to restart an operation. Normally, a counter is only cleared after stopping (disabling) and reading
the counter. If you clear a counter while it is enabled, it continues to count incoming pulses so the counter value
may not remain at zero.
21.
Stop (disable) the counter.
Counter 0:
Counter 1:
outp(base+15,0x08);
outp(base+15,0x88);
22.
Read the data (optional).
The value is returned in 3 bytes, low, middle, and high (2 bytes for counter 1).
Counter 0:
Counter 1:
low=inp(base+12);
low=inp(base+12);
middle=inp(base+13);
high=inp(base+13);
high=inp(base+14);
23.
Clear the counter.
Counter 0:
Counter 1:
outp(base+15,0x01);
outp(base+15,0x81);