Athena III User Manual Rev A.03
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Page
75
20.3
Command Sequences
Diamond Systems provides driver software to control the counter/timers on Athena III. The information in this
section is intended as a guide for programmers writing their own code, instead of using the driver, and to give a
better understanding of the counter/timer operation.
The counter control register is located at I/O address base+15.
20.3.1
Load and Enable (Run) a Counter Sequence
14.
Write the data to the counter. For counter 0, three bytes are required to load a 24-bit value. For counter
1, two bytes are needed for a 16-bit value. The value is an unsigned integer.
Break the load value into 3 bytes: low, middle, and high, (Two bytes for Counter 1) and write the bytes to
the data registers in any sequence.
Counter 0:
Counter 1:
outp(base+12,low);
outp(base+12,low);
outp(base+13,middle);
outp(base+13,high);
outp(base+14,high);
15.
Load the counter.
Counter 0:
Counter 1:
outp(base+15,0x02);
outp(base+15,0x82);
16.
Enable the gate if desired. The gating may be enabled or disabled at any time. When gating is disabled,
the counter counts all incoming edges. When gating is enabled, if the gate is high the counter counts all
incoming edges and, if the gate is low, the counter ignores incoming clock edges.
Counter 0:
Counter 1:
outp(base+15,0x10);
outp(base+15,0x90);
17.
Enable the counter. A counter may be enabled or disabled at any time. If disabled, the counter ignores
incoming clock edges.
Counter 0:
Counter 1:
outp(base+15,0x04);
outp(base+15,0x84);
20.3.2
Read a Counter Sequence
18.
Latch the counter.
Counter 0:
Counter 1:
outp(base+15,0x40);
outp(base+15,0xC0);
19.
Read the data.
The value is returned in 3 bytes, low, middle, and high (2 bytes for counter 1).
Counter 0:
Counter 1:
low=inp(base+12);
low=inp(base+12);
middle=inp(base+13);
high=inp(base+13);
high=inp(base+14);
20.
Assemble the bytes into the complete counter value.
Counter 0:
Counter 1:
val = high * 216 + middle * 28 + low;
val = high * 28 + low;