Diamond Systems Athena III User Manual Download Page 7 | Manualshive

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Diamond Systems Athena III User Manual Download Page 7

Athena III User Manual Rev A.03

www.diamondsystems.com

Page

7

2. INTRODUCTION

Athena III is an embedded single-board computer (SBC) in a custom PC/104 small form factor that integrates a
complete embedded PC and data acquisition circuitry into a single board.

The  Athena  III  SBC  is  based  on  an  Intel  E-Series  CPU  with  onboard  central  processing,  memory  and  memory
management  devices  and  I/O  management  for  specific  functions.    The  board  is  larger  than  the  PC/104  PCB
format  on  three  sides  but  uses  the  PC/104  mounting  method  and  interface  specification.    The  Athena  III  SBC
includes the following additional features.

Communicates externally over the ISA bus and I/O ports

Generates on-board RGB video for CRT display systems

Contains LVDS formatting to drive a flat panel

Is powered from an externally reg5VDC supply

Four standard models of Athena III are available as shown in the following table.

Model

Processor Speed

RAM Size

Data Acquisition

ATHE1000A-1G

1GHz

1GB

Yes

ATHE1000D-1G

1GHz

1GB

DIO only

ATHE1600A-1G

1.6GHz

1GB

Yes

ATHE1600D-1G

1.6GHz

1GB

DIO only

The  Athena  III  SBC  uses  the  ISA  bus,  internally,  to  connect  serial  ports  1  through  4  and  the  data  acquisition
circuit  to  the  processor.  The  ISA  bus  is  brought  out  to  an  expansion  connector  to  mate  with  add-on  boards.
Diamond  Systems  manufactures  a  wide  variety  of  compatible  PC/104  add-on  boards  for  analog  I/O,  digital  I/O,
counter/timer functions, serial ports and power supplies.

Description and Features

The Athena III single board computer includes the following key system and data acquisition features.

2.1

Functions

The functions listed below are applicable for all models.

Intel Atom E6xxT

“Tunnel Creek” processors (Queensbay platform), clocked at 1.0GHz or 1.6GHz

1GB soldered DDR2 DRAM on 8 devices (533 or higher speed)

1 Gigabit Ethernet port on pin header, with on-board magnetics

4 USB 2.0 ports on headers

4 serial ports, all with RS-232/422/485 capability. COM1/COM2 and COM3/COM4 are always set to

the same protocol in pairs. Individual protocol selection for each port is not available.

USB flashdisk mounting location

USB client

LVDS flat panel interface up to 1280 x 768 maximum resolution

VGA interface up to 1600 x 1200 maximum resolution

1 SATA port

24 digital I/O lines ( provided by LPC-ISA FPGA )

Programmable blue LED on board to indicate system status

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Summary of Contents for Athena III

Page 1: ...sition Rev A 03 May 2014 Revision Date Comment A 03 5 16 2014 Minor version Copyright 2014 FOR TECHNICAL SUPPORT Diamond Systems Corporation PLEASE CONTACT 555 Ellis Street Mountain View CA 94043 USA...

Page 2: ...ces 11 3 2 6 Connecting Power 11 3 2 7 Display 11 3 3 BOOTING THE SYSTEM 12 3 3 1 BIOS Setup 12 3 3 2 Operating System Drivers 12 4 FUNCTIONAL OVERVIEW 13 4 1 FUNCTIONAL BLOCK DIAGRAM 13 4 2 FUNCTIONA...

Page 3: ...37 8 4 BACKUP BATTERY 37 8 5 SYSTEM RESET 37 9 BIOS 38 9 1 BIOS SETTINGS 38 9 1 1 Serial Ports 38 9 1 2 Parallel Port 38 9 1 3 LCD Video Settings 38 9 1 4 Miscellaneous Settings 38 9 2 BIOS CONSOLE RE...

Page 4: ...69 16 4 1 D A Conversion Formulas for Unipolar Output Ranges 69 16 4 2 D A Conversion Formulas for Bipolar Output Ranges 70 17 GENERATING AN ANALOG OUTPUT 71 17 1 COMPUTE THE D A CODE FOR THE DESIRED...

Page 5: ...edge to avoid possible shorting from this type of damage However these design rules are not sufficient to prevent damage in all situations A third cause of failure is when a metal screwdriver tip slip...

Page 6: ...acceptable range of voltages connected to digital I O signals is 0 5V and they can withstand about 0 5V beyond that 0 5 to 5 5V before being damaged However logic signals at 12V and even 24V are comm...

Page 7: ...ly The Athena III SBC uses the ISA bus internally to connect serial ports 1 through 4 and the data acquisition circuit to the processor The ISA bus is brought out to an expansion connector to mate wit...

Page 8: ...counter timer for A D sample rate control event counting and programmable interrupts Auto calibration with Universal Driver software support for all data acquisition functions 2 3 Expansion Options US...

Page 9: ...receive the product as part of Diamond s Athena III Development Kit which provides everything needed to ensure rapid application development This section of the Athena III User Manual covers basic har...

Page 10: ...thena III Cable Kit number C ATHE KIT provides convenient access to most of Athena III s I O features The kit s cable assemblies are shown in the photo below and identified in the table that follows I...

Page 11: ...board and mouse connectors into the appropriate connectors on the Main I O cable in the Athena III Cable Kit cable number C PRZ 01 Connect the end of the cable into connector J18 on Athena III 3 2 4 U...

Page 12: ...s other hardware and software parameters Options configurable via Setup typically include Number and type of mass storage devices Boot device priority Video display type and resolution IDA SATA serial...

Page 13: ...II s core embedded computer circuit features the ultra low power Intel Atom Queensbay extended temperature platform consisting of an Atom processor Tunnel Creek with I O Hub Topcliff The rest of the c...

Page 14: ...th capacity up to 8GB 4 2 6 Serial Ports Athena III provides four serial ports with varying protocols and signal availability The SCH3114 provides two of the serial ports The other two serial ports ar...

Page 15: ...nd enable use of an external battery instead External battery voltage requirement is 3 3V 10 4 2 11 Watchdog Timer A programmable watchdog timer WDT is included to provide an automatic reset in case o...

Page 16: ...PTION The figure below shows the Athena III SBC layout with connector and jumper block locations labeled On the following page is a figure showing the key dimensions on the Athena III PCB in millimete...

Page 17: ...Athena III User Manual Rev A 03 www diamondsystems com Page 17...

Page 18: ...A B J11 PC 104 ISA bus C D J14 USB flashdisk J15 USB 0 1 J16 USB 2 3 J17 USB Client Port Utility J18 Main I O serial ports PS 2 keyboard mouse parallel port utility J21 Input Power J23 Data Acquisitio...

Page 19: ...he LEDs found on the Athena III SBC LED Number Description Color LED46 DAQ FPGA loaded successfully Blue LED1 SATA activity Green LED2 Ethernet activity Green LED3 Ethernet Link 100Mbps Green LED4 Eth...

Page 20: ...external battery for maintaining the Real Time Clock and the CMOS settings BIOS settings for various system configurations The battery voltage for this input should be 3 3 6VDC The current draw averag...

Page 21: ...J5 Connector J5 is a 2x4 pin header for connecting a VGA monitor Green 1 2 Red Blue 3 4 Ground HSYNCE 5 6 DDC data VSYNC 7 8 DDC clock Signal Definition Ground Ground return Red RED signal positive 0...

Page 22: ...21 22 Scan Direction LVDS data 1 23 24 LVDS Map Ground 25 26 Ground VDD LCD display 27 28 VDD LCD display VDD LCD display 29 30 VDD LCD display Signal Definition LVDS Data 0 2 Primary Data Channel bit...

Page 23: ...embedded microcontroller or by pin 6 on this connector A jumper selects the source of the brightness signal to this pin Connector on board Molex 53047 0610 or equivalent Mating Cable Connector Molex...

Page 24: ...15 SD1 A8 B8 ENDXFR LA18 C7 D7 IRQ14 SD0 A9 B9 12V LA17 C8 D8 DACK0 IOCHRDY A10 B10 Key MEMR C9 D9 DRQ0 AEN A11 B11 SMEMW MEMW C10 D10 DACK5 SA19 A12 B12 SMEMR SD8 C11 D11 DRQ5 SA18 A13 B13 IOW SD9 C1...

Page 25: ...J15 J16 Connectors J15 USB 0 1 and J16 USB 2 3 provide four USB 2 0 ports The connectors have identical pinouts as described below J15 J16 USB Connectors Key pin cut 1 2 Shield GND 3 4 GND USB1 3 D 5...

Page 26: ...Power switch Reset switch Power and HDD LEDs J18 Main I O Connector COM1 COM4 signals depend on the selected protocol The pinout shown on the next page is for RS 232 For RS 422 or RS 485 the following...

Page 27: ...CTS2 15 15 PD6 DTR2 16 16 GND RI2 17 17 PD7 GND 18 18 GND COM3 DCD3 19 19 ACK DSR3 20 20 GND RXD3 21 21 BUSY RTS3 22 22 GND TXD3 23 23 PE CTS3 24 24 GND DTR3 25 25 SLCT RI3 26 26 KB Clk KYBD GND 27 2...

Page 28: ...nects to pin 1 of the PS 2 connector KB MS V Power pin connects to pin 4 of the PS 2 connector Utilities A 5V Out Switched power pin that is turned on and off with the ATX power switch or with the 5V...

Page 29: ...er In particular many disk drives need extra current during startup If your system fails to boot properly or if disk accesses do not work properly the first thing to check is the power supply voltage...

Page 30: ...7 DIO B0 9 10 DIO B1 DIO B2 11 12 DIO B3 DIO B4 13 14 DIO B5 DIO B6 15 16 DIO B7 DIO C0 17 18 DIO C1 DIO C2 19 20 DIO C3 DIO C4 GATE0 21 22 DIO C5 GATE1 DIO C6 CLK1 23 24 DIO C7 OUT0 EXTTRIG 25 26 TOU...

Page 31: ...ly Do not connect to external supply DGND Digital ground 0V reference used for digital circuitry only AGND Analog ground used for analog circuitry only Vout pin is for analog outputs Vin pin is for an...

Page 32: ...k with Default Settings Jumper Location Function Pins 1 2 Pins 2 3 Pins 5 6 Pins 6 7 LCD VDD set to 5V default LCD VDD set to 3 3V Backlight inverter VDD set to 5V default Backlight inverter VDD set t...

Page 33: ...fault A D X X default X Note IRQ4 can only be used for the data acquisition circuit if it is not already used for COM3 It is possible to set up all three circuits to share either IRQ4 or IRQ5 However...

Page 34: ...input uses two wires input and ground The measured input voltage is the difference between these two wires A differential input uses three wires input input and ground The measured input voltage is th...

Page 35: ...bipolar both positive and negative input voltages For unipolar inputs install a jumper as shown below For bipolar inputs omit the jumper The default configuration is bipolar mode jumper out A D Unipol...

Page 36: ...PC 104 Plus cards that are in the system These settings may also vary depending on what other devices are present in the system For example adding a PC 104 Plus card may change the on board Ethernet...

Page 37: ...bottom for Continue C R after POST select Off default to turn off after POST or select On to remain on always 4 Exit the BIOS and save your settings 8 3 Flash Memory Athena III contains a 2048KB 16 b...

Page 38: ...Type This setting defaults to 7 Do not alter this setting unless specifically instructed to do so This setting affects the LCD display modes supported mode 7 is the only setting currently supported No...

Page 39: ...spend to RAM Memory Shadow These parameters should only be modified by advanced users These settings can adversely affect system performance and reliability 9 2 BIOS Console Redirection Settings For a...

Page 40: ...not required Additional software support includes a packet driver with software to allow a full TCP IP implementation 10 2 Serial Ports Athena III contains four serial ports Each port is capable of tr...

Page 41: ...sequence in the BIOS so the system boots from CD ROM first 2 Insert the Windows installation CD into the CD ROM and restart the computer 3 Follow the manufacturer s instructions for installing Window...

Page 42: ...a 16 bit counter timer for user applications High speed A D sampling is supported with interrupts and a FIFO The FIFO is used to store a user selected number of samples and the interrupt occurs when t...

Page 43: ...ided the board is in enhanced mode Page 0 Base Write Function Read Function 0 Command A D LSB 1 Enhanced mode control A D MSB 2 A D channel A D channel 3 A D gain page select scan settings A D gain an...

Page 44: ...B4 B3 B2 B1 B0 10 C7 C6 C5 C4 C3 C2 C1 C0 11 DIOCTR DASIM DIRA DIRCH DIRB DIRCL Page 0 Read Register Summary Base 7 6 5 4 3 2 1 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 AD15 AD14 AD13 AD12 AD11 AD10 AD9...

Page 45: ...4 D3 D2 D1 D0 13 A7 A6 A5 A4 A3 A2 A1 A0 14 TDBUSY EEBUSY CALMUX 15 0xA1 Page 2 Write Register Summary Base 7 6 5 4 3 2 1 0 12 EXFIFO 13 DACPOLE N DACPOL ADPOL ADPOLEN ADSD ADSDEN 14 SCANINT 15 DAQ_LE...

Page 46: ...ggered by writing to this bit Instead the A D will be triggered by a signal selected by ADCLK in base 4 bit 5 RSTBRD Reset the entire board excluding the D A Writing a 1 to this bit causes all registe...

Page 47: ...e combined into a single formula for efficiency Base 1 Write Enhanced Features Access Register Bit No 7 6 5 4 3 2 1 0 Name PG1 PG0 Reset 0 0 0 0 0 0 0 0 This register has dual function When 0xA5 and 0...

Page 48: ...og input circuit is settling During this time an A D conversion should not be performed because the data will be inaccurate After writing a new gain setting Base 3 the ADWAIT bit is also set and the p...

Page 49: ...l is HIGH The STS bit stays high during the A D conversion ADG1 0 Analog input gain The gain is the ratio of the voltage seen by the A D converter and the voltage applied to the input pin The gain set...

Page 50: ...the gain register Base 3 is changed It stays high for 9 microseconds The program should monitor this bit after writing to either register and wait for it to become 0 prior to starting an A D conversi...

Page 51: ...1 0 internal clock output from counter timer 0 1 external clock input EXTTRIG DMAEN Enable DMA operation 1 enable 0 disable TINTE Enable timer interrupts 1 enable 0 disable DINTE Enable digital I O i...

Page 52: ...ically to 1024 The interrupt routine is responsible for reading the correct number of samples out of the FIFO The interrupt rate is equal to the total sample rate divided by the FIFO threshold General...

Page 53: ...Register Description for Page 2 Base 12 Current FIFO depth MSB This value indicates the upper 4 bits of the number of A D values currently stored in the FIFO OVF FIFO Overflow bit This bit indicates...

Page 54: ...pt status 1 interrupt pending 0 interrupt not pending AINT Analog input interrupt status 1 interrupt pending 0 interrupt not pending ADCH3 0 Current A D channel This is the channel that will be sample...

Page 55: ...A 4 PC7 Out 0 DIO NOTE If DIOCTR 1 then the pin direction is controlled by DIRCH This bit resets to 1 DIRA Port A direction 0 output 1 input DIRB Port B direction 0 output 1 input DIRCH Port C bits 7...

Page 56: ...e byte for counter 0 When writing to this register an internal load register is loaded Upon issuing a Load command through Base 15 the selected counter s associated register will be loaded with this v...

Page 57: ...d Base 13 Any data in Base 14 will be from the previous Counter 0 access GTDIS Disable external gating for the selected counter GTEN Enable external gating for the selected counter If enabled the asso...

Page 58: ...2 1 0 Name EE_EN EE_RW RUNCAL CALMUX TDACWR X X X This register is used to initiate various commands related to autocalibration EE_EN EEPROM Enable Writing a 1 to this bit will initiate a transfer to...

Page 59: ...s register each time after any change in the states of registers bits PG1 and PG0 base 1 bits 1 0 in order to get access to the EEPROM This helps prevent accidental corruption of the EEPROM contents O...

Page 60: ...g 0 unipolar mode 1 bipolar mode Unipolar output setting 0 bipolar mode 1 unipolar mode ADPOLEN Enable ADPOL When this bit is set the ADPOL setting is output to the DAC circuit ADSD Single ended diffe...

Page 61: ...ain setting for the inputs which causes them to be amplified before they reach the A D converter The gain setting is controlled in software which allows it to be changed on a channel by channel basis...

Page 62: ...0 to base 2 The first conversion is on channel 0 the second will be on channel 1 and the third will be on channel 2 The channel counter wraps around to the beginning so the fourth conversion will be o...

Page 63: ...eted return 1 conversion did not complete 14 7 Read the Data from the Board Once the conversion is complete you can read the data back from the A D converter The data is a 16 bit value and is read bac...

Page 64: ...ep is not included here Only conversion to input voltage is described However you can combine both transformations into a single formula if desired To convert the A D value to the corresponding input...

Page 65: ...Input voltage 17761 32768 65536 5V 3 855V For a unipolar input range 1 LSB 1 65536 Full scale voltage The following table illustrates the relationship between A D code and input voltage for a unipolar...

Page 66: ...to an integral number of scans For example if the scan size is 8 channels the FIFO threshold should be set to 8 16 24 32 40 or 48 but not less than 8 This way the interrupt will occur at the end of t...

Page 67: ...ccurs The user program monitors STS Base 3 bit 7 and reads A D data when STS goes low 1 0 Single A D conversions are triggered by the source selected with ADCLK Base 4 bit 4 STS stays high during the...

Page 68: ...ena III computer hardware to an analog signal terminating at an external source 16 2 Resolution The resolution is the smallest possible change in output voltage For a 12 bit DAC the resolution is 1 2...

Page 69: ...nipolar mode 0 10V and Full scale range 10V 0V 10V if Desired output voltage 2 000V D A code 2 000V 10V 4096 819 2 819 Note the output code is always an integer For the unipolar output range 0 10V 1 L...

Page 70: ...scale range 10V 10V 20V if Desired output voltage 2 000V D A code 2V 10V 2048 2048 2457 6 2458 For the bipolar output range 10V 1 LSB 1 4096 20V or 4 88mV The following table illustrates the relation...

Page 71: ...mpute the LSB and MSB values LSB D A Code 255 keep only the low 8 bits MSB int D A code 256 strip off low 8 bits keep 4 high bits Example For Output code 1776 Compute LSB 1776 255 240 0xF0 and MSB int...

Page 72: ...ith 16 bit accuracy exhibit gain and offset errors that vary depending on the gain setting The settings that work best for one range may not be sufficient to calibrate another If a circuit is calibrat...

Page 73: ...located at pins 1 through 24 on the I O header J14 The lines are 3 3V and 5V logic compatible Each output is capable of supplying 8mA in logic 1 state and 12mA in logic 0 state DIRA DIRB DIRCH and DIR...

Page 74: ...cept that it is a 16 bit counter Counter 1 also has an input a gate and an output These signals may be user provided on the I O header when DIOCTR is 0 or the input may come from the on board clock ge...

Page 75: ...e outp base 13 high outp base 14 high 15 Load the counter Counter 0 Counter 1 outp base 15 0x02 outp base 15 0x82 16 Enable the gate if desired The gating may be enabled or disabled at any time When g...

Page 76: ...eared after stopping disabling and reading the counter If you clear a counter while it is enabled it continues to count incoming pulses so the counter value may not remain at zero 21 Stop disable the...

Page 77: ...1GB to 8GB of solid state non volatile memory that operates like an USB drive without requiring additional driver software support Model Capacity FDU 1G XT 1GB FDU 2G XT 2GB FDU 4G XT 4GB FDU 8G XT 8G...

Page 78: ...option to view or modify the BIOS settings for the desired configuration area The screens displayed for each area are described below The following keyboard controls are available on any page for nav...

Page 79: ...Version 4 6 3 7 Project Version 0DATH 0 12 Build Date 09 07 2012 19 18 24 Product Name Athena III Motherboard Manufacturer Diamond Systems MRC Version 01 00 Total Memory 1024 MB DDR2 Platform Informat...

Page 80: ...Configuration South Bridge Chipset Configuration IOH Configuration Boot Boot Configuration Quiet Boot Disabled Fast Boot Disabled Setup Prompt Timeout 1 Bootup NumLock State On CSM16 Module Version 0...

Page 81: ...Save Exit Boot to Windows CE Save Changes and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Save Changes Discard Changes Restore Defaults Save as User Def...

Page 82: ...age interfaces 1 SATA pin header USB flashdisk solid state USB module supports up to 8GB and mounts to SBC Keyboard mouse PS 2 Audio AC 97 Line in Line Out Mic 23 2 Data Acquisition Circuitry Analog i...

Page 83: ...voltage Logic 0 0 0V min 0 33V max Logic 1 2 4V min 5 0V max Output current Logic 0 12mA max per line Logic 1 4mA max per line A D Pacer clock 24 bit down counter source 10MHz 1MHz or external signal...

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