Athena III User Manual Rev A.03
www.diamondsystems.com
Page
54
Base + 7
Write
DAC MSB
Bit No.
7
6
5
4
3
2
1
0
Name
DACH1
DACH0
-
-
DA11
DA10
DA9
DA8
Reset
0
0
0
0
0
0
0
0
DACH1
–0 D/A channel. The values written to Base + 6 and Base + 7 update the selected channel
immediately unless DASIM is enabled. The update takes approximately 50ns due to the DAC
serial interface.
DA11
–8
D/A bits 11 - 8; DA11 is the MSB. D/A data is an unsigned 12-bit value. Writing to this register
updates the DAC (If DASIM is disabled).
Base + 7
Read
Analog Operation Status
Bit No.
7
6
5
4
3
2
1
0
Name
-
TINT
DINT
AINT
ADCH3
ADCH2
ADCH1
ADCH0
Reset
0
0
0
0
0
0
0
0
TINT
Timer interrupt status, 1 = interrupt pending, 0 = interrupt not pending.
DINT
Digital I/O interrupt status, 1 = interrupt pending, 0 = interrupt not pending.
AINT
Analog input interrupt status, 1 = interrupt pending, 0 = interrupt not pending.
ADCH3-0 Current A/D channel. This is the channel that will be sampled on the
next
conversion.
When any of the bits 6
–4 are 1, the corresponding circuit is requesting interrupt service. The interrupt routine
must poll these bits to determine which circuit needs service and then act accordingly.
Base + 8
Read / Write
Digital I/O Port A
Bit No.
7
6
5
4
3
2
1
0
Name
A7
A6
A5
A4
A3
A2
A1
A0
Reset
0
0
0
0
0
0
0
0
These registers are used for digital I/O on PortA. The direction of each register is controlled by the DIO control
register at Base+11.
Base + 9
Read / Write
Digital I/O Port B
Bit No.
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Reset
0
0
0
0
0
0
0
0
These registers are used for digital I/O on PortB. The direction of each register is controlled by the DIO control
register at Base+11.