Athena III User Manual Rev A.03
www.diamondsystems.com
Page
55
Base + 10
Read / Write
Digital I/O Port C
Bit No.
7
6
5
4
3
2
1
0
Name
C7
C6
C5
C4
C3
C2
C1
C0
Reset
0
0
0
0
0
0
0
0
These registers are used for digital I/O on PortC. The direction of each register is controlled by the DIO control
register at Base+11.
Base + 11
Write
Digital I/O and DA Control Register
Bit No.
7
6
5
4
3
2
1
0
Name
DIOCTR
DASIM
DIRA
DIRCH
-
DIRB
DIRCL
Reset
1
X
0
1
1
0
1
1
DIOCTR
Selects counter I/O signals or digital I/O lines PL3B(7), PL3A(6), PL2B(5), PL2A(4) on the FPGA
pins (Pins 21-24 on J23):
Pin No.
DIOCTR = 0 DIOCTR = 1
PL3B(7)
PC4Gate 0 DIO
PL3A(6)
PC5Gate 1 DIO
PL2B(5)
PC6 Clk 1 DIO
PL2A(4)
PC7 Out 0 DIO
NOTE:
If DIOCTR = 1, then the pin direction is controlled by DIRCH.
This bit resets to 1.
DIRA
Port A direction. 0 = output, 1 = input
DIRB
Port B direction: 0 = output, 1 = input
DIRCH
Port C bits 7-4 direction: 0 = output, 1 = input
DIRCL
Port C bits 3-0 direction: 0 = output, 1 = input
DASIM
DASIM D/A simultaneous update control. This bit determines when the D/A is updated.
0 = When Base+7 is written, the D/A data is loaded into the D/A and the update command is
sent immediately afterwards.
1 = When Base+7 is written, the 12bit DA values will be loaded into the D/A converter but the
update command will not be issued. Instead, a read of the register at Page 2, Base+15 will cause
the update of the D/A converter.
Base + 11
Read
Digital I/O and DA Control Register Readback
Bit No.
7
6
5
4
3
2
1
0
Name
-
-
DASIM
DIRA
DIRCH
-
DIRB
DIRCL
Reset
0
0
0
0
0
0
0
0
Read-back of Base+11.