Athena III User Manual Rev A.03
www.diamondsystems.com
Page
60
ADC Control: Base+13 (Read/Write)
Bit:
7
6
5
4
3
2
1
0
Name:
0
0
DACPOLEN DACPOL
ADPOL ADPOLEN
ADSD
ADSDEN
DACPOLEN
DACPOL
ADPOL
Enable DACPOL. When this bit is set the DACPOL setting is output to the DAC circuit.
DAC polarity setting; 0 = unipolar mode; 1 = bipolar mode.
Unipolar output setting; 0 = bipolar mode; 1 = unipolar mode.
ADPOLEN
Enable ADPOL. When this bit is set the ADPOL setting is output to the DAC circuit.
ADSD
Single-ended/differential mode setting; 0 = differential mode; 1 = single ended mode.
ADSDEN
Enable ADSD. When this bit is set the ADSD setting is output to the DAC circuit.
Page 2 Select Read Back Check: Base+15 (Read)
Bit:
7
6
5
4
3
2
1
0
Name:
PG2ID
PGID
Register page 2 ID. This register always contains the value 0xA2.