Athena III User Manual Rev A.03
www.diamondsystems.com
Page
22
6.5
LCD Panel, LVDS Interface (J7)
Connector J7 provides access to the internal LVDS LCD display drivers. See below for connector J8 for LCD
backlight information. The LCD panel power is jumper-selectable for 3.3V (default) or 5V. The Intel Atom E-Series
CPU has maximum allowable LCD support of 1280 x 768.
Ground
1
2
Ground
LVDS clock-
3
4
LVDS clock+
5
6
Ground
7
8
Ground
LVDS data 0-
9
10 LVDS data 3+
LVDS data 0+ 11
12 LVDS data 3-
Ground 13
14 Ground
LVDS data 2- 15
16
LVDS data 2+ 17
18
Ground 19
20 Ground
LVDS data 1+ 21
22 Scan Direction
LVDS data 1- 23
24 LVDS Map
Ground 25
26 Ground
VDD (LCD display) 27
28 VDD (LCD display)
VDD (LCD display) 29
30 VDD (LCD display)
Signal
Definition
LVDS Data 0-2 +/-
Primary Data Channel, bits 0-2 (LVDS Differential signaling)
LVDS Clock +/-
Primary Data Channel, Clock (LVDS Differential signaling)
LVDS Data 0-2 +/-
Secondary Data Channel, bits 0-2 (LVDS Differential signaling)
LVDS Clock +/-
Secondary Data Channel, Clock (LVDS Differential signaling)
VDD
+3.3V Switched Power Supply for LCD display
(only powered up when LCD display is active)
Ground
Power Ground, 0V
Connector on board:
JST model number BM30B-SRDS-G-TF or equivalent
Mating cable connector:
JST model number SHDR-30V-S-B or equivalent
Terminals:
JST model number SSH-003GA-P0.2 or equivalent
J7 LCD Panel Connector (end view)