Denon AVR-S710W, Service Manual

Page: 133 / 169

MC14094BDTR2G (DIGITAL_MCU : IC753)
Block diagram
Terminal Functions
Symbol I/O Pu/Pd
Lv
Cnv STBY STOP
CEC
STBY
Function
Q1 HPD1 L L L Hot-Plug-Detect (HDMI) control pin
Q2 HPD2 L L
L Hot-Plug-Detect (HDMI) control pin
Q3 HPD3 L L
L Hot-Plug-Detect (HDMI) control pin
Q4 HPD4 L L L Hot-Plug-Detect (HDMI) control pin
Q5 HPD5 L L L Hot-Plug-Detect (HDMI) control pin
Q6 HPD6 L L
L Hot-Plug-Detect (HDMI) control pin
Q7 VIN A L L
L COMPOSITE VIDEO SELECT IC(NJM2595) control pin
Q8 VIN B L L L COMPOSITE VIDEO SELECT IC(NJM2595) control pin
MC14094B
http://onsemi.com
2
13
14
15
16
9
10
11
12 5
4
3
2
1
8
7
6
Q7
Q6
Q5
OUTPUT
ENABLE
V
DD
Q
S
Q
′
S
Q8
Q1
CLOCK
DATA
STROBE
V
SS
Q4
Q3
Q2
PIN ASSIGNMENT
TRUTH TABLE
Clock
Output
Enable
Strobe Data
Parallel Outputs Serial Outputs
Q1 Q
N
Q
S
* Q
′
S
0 X X Z Z Q7 No Chg.
0 X X Z Z No Chg. Q7
1 0 X No Chg. No Chg. Q7 No Chg.
1 1 0 0 Q
N
−
1 Q7 No Chg.
1 1 1 1 Q
N
−
1 Q7 No Chg.
1 1 1 No Chg. No Chg. No Chg. Q7
Z = High Impedance X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q
S
.
ORDERING INFORMATION
Device Package Shipping
†
MC14094BCPG PDIP
−
16
(Pb
−
Free)
500 Units / Rail
MC14094BDG SOIC
−
16
(Pb
−
Free)
48 Units / Rail
MC14094BDR2G
SOIC
−
16
(Pb
−
Free)
2500 Units / Tape & Reel
NLV14094BDR2G*
MC14094BDTR2G
TSSOP
−
16
(Pb
−
Free)
2500 Units / Tape & Reel
NLV14094BDTR2G*
MC14094BFELG SOEIAJ
−
16
(Pb
−
Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC
−
Q100 Qualified and PPAP
Capable.
MC14094B
http://onsemi.com
5
3 − STATE TEST CIRCUIT
FOR t
PHZ
AND t
PZH
V
SS
FOR t
PLZ
AND t
PZL
V
DD
R1
OUTPUT
50 pF
O.E.
CLOCK
ST
DATA
Figure 1.
R1 = 1 k = t
PHL
, t
PLH
R1 = 10 k = t
PHZ
, t
PZH
, t
PLZ
, t
PZL
REGISTER STAGE 1
BLOCK DIAGRAM
LATCH 1 3-STATE BUFFER 1
15
2
SERIAL
DATA IN
OUTPUT
ENABLE
CLOCK CLOCK STROBE
CLOCK
CLOCK CLOCK
CLOCK
STROBE STROBE
STROBE
V
DD
4
5
6
7
14
13
12
11
10
9
Q1
Q2
Q
′
S
Q3
Q4
Q5
Q6
Q7
Q8
Q
S
2
3
4
5
6
7
8
REGISTER STAGE 2
REGISTER STAGE 3
REGISTER STAGE 4
REGISTER STAGE 5
REGISTER STAGE 6
REGISTER STAGE 7
REGISTER STAGE 8
LATCH 2
LATCH 3
LATCH 4
LATCH 5
LATCH 6
LATCH 7
LATCH 8
3-STATE BUFFER�2
3-STATE BUFFER�3
3-STATE BUFFER�4
3-STATE BUFFER�5
3-STATE BUFFER�6
3-STATE BUFFER�7
3-STATE BUFFER�8
CLOCK CLOCK
STROBE STROBE
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
STROBE
STROBE
CLOCK
STROBE
3
1
*Input Protection Diodes
*
*
*
*
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