Data Translation DT3152-LS, User Manual

Page: 35 / 214

Principles of Operation
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Note:
According to sampling theory (Nyquist Theorem), specify a
frequency that is at least twice as fast as the input’s highest
frequency component. This prevents an error condition called
aliasing, in which high frequency input components erroneously
appear as lower frequencies after sampling. For example, to
accurately sample a 20 kHz signal, specify a sampling frequency of
at least 40 kHz.
Using the Digital Clock Sync Circuitry, which has no more than ±4 ns
jitter, the DT3152-LS board synchronizes the pixel clock to the first
frame of an asynchronous external video source. Synchronization
occurs when a horizontal sync is received or is inserted.
The DT3152-LS board supports an internal and external pixel clock,
as described in the following sections.
Internal Pixel Clock
The DT3152-LS board provides a programmable pixel clock that
generates the base frequency for video input timing. The clock is
subsequently phase adjusted and divided down to produce the
desired digitization rate.
You can program the pixel clock for any frequency from 1 kHz to
20 MHz, limited by the granularity of the pixel clock controller. For
area-scan operations, the default frequency is 12.5 MHz for 60 Hz
image formats and 15 MHz for 50 Hz image formats. For line-scan
operations, the default frequency is 1 MHz.
Note: For line-scan operations, the internal pixel clock drives the
master clock output signals (MCLK_OUT
−
and M),
described on page 31 .