Data Translation DT3152-LS, User Manual

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Chapter 2
32
For example, if you set the edge of the integration output pulse to
low-to-high and the pixel clock value to 4095 and then set the
edge of the integration output pulse to high-to-low and the pixel
clock value to 5000, the integration output signal goes high at
pixel count 4095 and goes low at pixel count 5000.
• Line-sync output signal
−
The line-sync output signal drives the
line-sync camera and controls the camera’s line rates. The video
signal from the camera is then digitized as usual, using the syncs
returned by the camera as the sync basis.
The DT3152-LS board generates RS-422 line-sync output signal
LINE_OUT
−
on pin 6 of connector J2 and line-sync output signal
LINE_OUT
+ ο
n pin 5 of connector J2.
Using software, you can specify the number of pixel clock pulses
that you want to occur before the specified edge (high-to-low or
low-to-high) of the line-sync pulse becomes active. If the
specified edge is high-to-low, the low portion of the pulse is
active; if the specified edge is low-to-high, the high portion of the
pulse is active.
For example, if you set the edge of the line-sync output pulse to
low-to-high and the pixel clock value to 5127 and then set the
edge of the line-sync output pulse to high-to-low and the pixel
clock value to 6000, the line-sync output pulse goes high at pixel
count 5127 and goes low at pixel count 6000.
With the falling edge of the line-sync output pulse, another line starts
and the pixel clock counter is reset to 0.
For both the integration output signal and the line-sync output
signal, if the maximum pixel count (8192) does not allow a long
enough period, you can use software to specify a clock divider to
change the period of the pulse. The clock divider ranges from 2
0
to
2
12
. The period of the integration output pulse (in seconds) is
calculated as follows:
output period = line length x clock divider x 1
clock frequency