Daewoo DTR-14D3VG, Service Manual

Page: 20 / 73

18
No Name Description
27 LUMINANCE in, The Luminance out, B-Y / R-Y out signals from the output pins from the device itself or
31 B-Y / R-Y in from YUV signal processing IC’s MUST be DC coupled to the Luminance in, B-Y / R-Y
32 inputs pin 27,31 and 32. Internally these pins are AC coupled to the input clamps.
The clamping action is slow to ensure optimal clamping perormance for noisy YUV sig-
nals. In case YUV signal processing IC’s are placed in the YUV path then be sure that
the maximum voltage (DC-level and peak video level)does not exceed 5.5V. The
TDA917X family IC’s meet this requirement.
When the output of a feature IC
exceeds the maximum DC-level of 5.5V then level shifters must be placed at the inputs
of the TDA884X. The Yin signal can be amplified, approximately 6dB, by means of the
I
2 C bit GAI in order to adapt to old feature IC’s like the TDA4565.
Because of the high input impedance outside burstkey clamping, it is advised to minimise
the track length to the Luminance in, B-Y / R-Y in pins. Adequate ground shielding of these
signal tracks is advised for good interference immunity. The TDA8840; TDA8841 and
TDA8842 only have Luminance out, B-Y/R-Y out signals and these signals are internally
connected to the Luminance in, B-Y/R-Y inputs. Also the GAI-bit is disabled in these types.
28 LUMINANCE in, The luminace output signal is approximately 1V
BLACK
-
WHITE
with typical output
29 B-Y / R-Y in impedance of 250
Ω
. The colour difference output signals (B-Y / R-Y) have
30 respectively a nominal output level 1.33V
PP
and 1.05V
PP
, the output impedance of pins
29 and 30 is 500
Ω
when a colour system is identified. The Luminance out and
B-Y/R-Y out signals can be connected to additional YUV signal processing IC’s.
How to connect these signals (AC or DC) depends on the input signals characteristic
of signal processing IC, at which these output signals are connected to.
33 SUBCARRIER The reference output can be used as a reference for comb filter applications.
Reference output (Fsc) For PCB layout considerations, a short signal track connection with interface devices is
advised. It is advised to minimise parasitic capacitance of pin to ground (i. e. avoid
large ground planes around signal track). The parasitic capacitance at this pin to
ground should be less than 10
P
F.
34 X-TAL 3.58 To ensure correct operation of both:
35 X-TAL 4.43 - colour processing internal circuits,
- sync calibration internal circuits,
it is only allowed to have 3.6MHz Xtals on pin34: both 4.4MHz,3.6MHz Xtals are
allowed on pin 35. If pin 35 is not used: then it is left open in application (also
XA,XB=O,1 ).
36 LOOP FILTER One of the important aspects of the PLL is the loop filter connected to pin 36;
PHASE it influences the dynamic performance of the loop.
DETECTOR
38 CVBS1
OUT
The output amplitude is 2Vpp (transfer gain ratio between CVBS
INT
or
CVBS
EXT
or CVBS/Y and CVBS1
OUT
is 2).
The maximum output impedance is 250
Ω
. For application with the SAA4961 combfil-
ter, 6dB attenuation is required. It is advised to use an emitter follower circuit as shown
in Fig 35. For scart application the same emitter follower can be used. It is advised that
the signal paths to the comb filter and back to the TDA8842 are as short as possible so
as to avoid crosstalk from interference sources.
The follower is placed as close as possible to pin 38.
39 BLACK PEAK For the correct working of the black stretcher an external time constant should
HOLD CAPACITOR be added at the black peak hold capacitor input.
40 HOR OUTPUT This open collector output is meant to drive the horizontal output stage.
The output is active low, i.e. the line transistor should conduct during the low
period of the output.
41 SANDCASTLE Pin 41 is a combined input/output pin.
OUTPUT/ The pin provides a three level sandcastle pulse.
FLYBACK INPUT Both burstkey pulse and vertical blanking pulse are always available, the line