Daewoo DTR-14D3VG, Service Manual

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The PHI-2 circuit shifts the horizontal drive, pin 40, such that the picture position on screen is constant.
The flyback input pin 41 is combined with the sandcastle output. This combined function provides a three level sand-
castle signal and is available starting with the highest level : burstkey, line blanking (=flyback pulse) and vertical blank-
ing.
Sandcastle waveform
The phase of the video signal with respect to the deflection current can be adapted by I 2 C bus Hs (horizontal shift, shift
picture left/rignt).
The PHI-2 loop filter is a first order filter. The capacitor is connected externally on pin 42.
• H-output and slow start/stop
The horizontal output is the driver pin for the line deflection. It is an open collector output. Under normal operation con-
dition the duty cycle of the output pulse is 45% off(Hout=high) / 55% on (Hout=low).
A build in slow start/stop circuit ensures a smooth start/stop behaviour of the line deflection and protects the line out-
put transistor.
During switch-on the horizontal output starts with the double frequency (31.25kHz) and with a duty cycle of 75% off
(Hout=high)/25% on (hout=low). After about 50ms the frequency is changed to the normal value (15.625kHz) and the
duty cycle to 45% off (Hout=high)/55% on (hout=low).
Also during switching-off via stand by (STB) the frequency is switched to the double value and the RGB drive is set to
maximum to discharge the voltage on the EHT capacitor to half of its maximum value. After about 100ms the RGB
drive is set to minimum and 50ms later the horizontal drive is switched-off.
Slow start / slow stop horizontal output
• Noise detector
The TDA884X has an internal noise detector. If the PHI-1 FOA/FOB is set to 00(Automatic mode) or 10(Gated
mode) the noise detector is used to switch the time constant of the horizontal PLL. The input of the detector is con-
nected to the selected CVBS input.
The noise detector measures the RMS value of the noise during a part of the sync pulse. (The detection level is
100m Vrms and corresponds to 20dB S/N-ratio for 1Vpp CVBS).
A field counter is used for hysteresis after 2 successive fields whether noise is detected. When noise is detected the
horizontal PLL time constant is switched to slow.