10
DW5255MBI
(TVTEXT 8-bit Micro controller, Rom-version)
=SDA5254 (SIEMENS Type No.)
(1) General Description
The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acquisition hardware modul, a display gener-
ator for “Level 1” TTX data and an 8 bit microcontroller running at 333 ns cycle time. The controller with dedicated hard-
ware guarantees flexibility, does most of the internal processing of TTX acquisition, transfers data to/from the external
memory interface and receives/transmits data via I
2
C and UART user interfaces. The block diagram shows the internal
organization of the SDA 525x. The Slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kbyte.
The microcontroller firmware does the total acquisition task (hamming- and parity-checks, page search and evaluation
of header control bits) once per field.
(2) Feature
• Acquisition:
- Feature selection via special function register
- Simultaneous reception of TTX, VPS and WSS
- Fixed framing code for VPS and TTX
- Acquisition during VBI
- Direct access to VBI RAM buffer
- Acquisition of packets X/26, X/27, 8/30 (firmware)
- Assistance of all relevant checks (firmware)
- 1-bit framing code error tolerance (switchable)
• Display:
- Features selectable via special function register
- 50/60 Hz display
- Level 1 serial attribute display pages
- Blanking and contrast reduction output
- 8 direct addressable display pages for SDA 5250, SDA 5254 and SDA 5255
- 1 direct addressable display pages for SDA 5251 and SDA 5252
- 12 x 10 character matrix
- 96 character ROM (standard G0 character set)
- 143 national option characters for 11 languages
- 288 characters for X/26 display
- 64 block mosaic graphic characters
- 32 characters for OSD in expanded character ROM + 32 characters inside OSD box
- Conceal/reveal
- Transparent foreground/background - inside/outside of a box
- Contrast reduction inside/outside of a box
- Cursor (colour changes from foreground to background colour)
- Flash (flash rate 1s)
- Programmable horizontal and vertical sync delay
- Full screen background colour in outer screen
- Double size / double width / double height characters
• Synchronization:
- Display synchronization to sandcastle or Horizontal Sync (HS) and Veritical Sync (VS) with start-stop-oscillator
- Independent clock systems for acquisition, display and controller
Summary of Contents for DTR-14D3VG
Page 5: ...3 Circuit Block Diagram...
Page 10: ...8 3 Block Diagram...
Page 66: ...64 1 14D3 Mechanical Exploded View...
Page 67: ...65 2 20D3...
Page 68: ...66 3 21D3...
Page 69: ...67 4 16D3...
Page 70: ...67 Printed Circuit Boards...
Page 71: ...Circuit Schematics CP 490 SCHEMATIC DIAGRAM...
Page 72: ...ENGINEER NOTE...