Daewoo DTR-14D3VG, Service Manual

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• Luminance signal processing
For luminance processing, the selected video signal is supplied to the H/V sync circuits for sync processing and also
to an adjustable delay line (Ons - 320ns, minimum step is 40ns, controlled via bus bits YD0-YD3).
The chroma trap is bypassed for no burst transmissions when in own intelligence mode (automode).
In Y/C modes the video signal follows a direct path with 160ns delay so as to ensure similarity with chroma path
delay.
The output signal is supplied to the peaking and coring stages whose operation is illustrated below.
The peaking function is realised with t = 160ns delay cells (i.e. frequency response reaches a maximum at a
frequency f = 1/2t = 3.125MHz).
The coring function has a non-linear transfer characteristic which implies that a noise suppression range (coring
range) of 15 IRE is realised. This means that extra noise introduced due to increased gain of the peak ng amplifier
is defeated by the coring function. The coring stage is activated via the I
2 C bus (COR).
Asymmetric peaking is introduced to enhance picture definition. The negative/positive overshoot ratio is
approximately 1.8.
The degree of peaking is controlled by the peaking amplifier via the I
2 C bus (PEAKING). The output of the peaking
amplifier is summed with the delayed (160ns) selected video signal. The output of the peaking/coring stages (i. e.
output of summing stage) is fed as internal luminance signal (Y
INT
) to the YUV selection circuit.
Colour Decoder
The main functions are:
- PLL/VCXO
- PAL/NTSC demodulation
- SECAM demodulation
- ASM (Automatic System Manager)
• PLL/VCXO
The PLL operates during the burstkey period; it generates a VCXO reference signal (f
VCXO
), in phaselock with the
incoming burst signal(f
BURST
).
Prior to lock condition, the signals f
VCSO
and f
BURST
are not synchronous and are present at phase detector input.
The loop filter averages the phase detector output current and the resulting control signal to the
VCXO is proportional to Sin(2
π∆
ft) where
∆
f = f
VCXO
– f
BURST
.
A lock situation occurs when
∆
f<VCXO holding range; once in lock, the phase detector output current is proportional
to
E
=
VCXO
-
BURST
(
E
is the static phase error).
The combined phase detector and VCXO sensitivity is high gain mode when a colour system is not yet identified.
For fast colour acquistion, the phase detector is in high gain mode when a colour system is not yet identfied.
The VCXO loop(not to be confused with phase locked loop, PLL) compensates for any attenuation loss or phase
shift in the crystal so that the it’s loop gain is unity and loop phase shift is zero. The VCXO reference outputs (0˚ and
90˚) are stable sinusoids.
VCXO oscillation is at series resonance of the selected Xtal. Since the PLL automatically tunes the VCXO to the
burst (if inside the PLL holding range) fine tuning of the VCXO with a trimming capacitance is not necessary.
The motional capacitance of the Xtal is damped by the internal resistance of the VCXO pins (i.e. 1K) in dorder to
realise the holding range.
The catching range (pull-in) of the PLL loop is governed by the PLL loop filter; the loop filter can be chosen so that
PLL holding and catching range are similar (direct catching).
The HUE phase rotator is inoperational when the PLL is active (i.e. no phase rotation during the burstkey period).
Outside the burstkey period, the hue control rotates the VCXO reference phases from -40˚ to 40˚ linearly for I2C bus
command (HUE:0 –>63).