S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
40
1.3.6.4 Setting Procedure
This section explains the setting procedure for the DualFlash mode.
In addition, writing to the DFCTRLR register is not possible when the DualFlash mode is enabled.
In order to perform writing to the DFCTRLR register again, issue a reset command.
1. Release a reset (disable the DualFlash mode)
2. JMP for programs other than those in the Flash area.
3. Set the DualFlash mode (DFCTRLR : WKEY="0xEACC", RME="0"/"1", DFE="1")
4. JMP for programs in the MainFlash area.
5. Set Flash Accelerator and trace buffer function
6. Set Access Size (DFASZR register) and Read Wait (DFRWTR register) of DualFlash area
7. Issue a reset command if changing the DualFlash mode setting
Notes:
−
Do not perform DualFlash mode settings after the trace buffer function is enabled (FBFCR : BE="1").
−
Do not perform DualFlash mode settings with instructions written in flash memory. Re-write programs other than
those in the Flash area.
−
Writing to the DFCTRLR register is invalid when the DualFlash mode is enabled (DFCTRLR : DFE="1"). In order to
perform writing again, issue a reset command.
−
Do not perform an access to the DualFlash area when the DualFlash mode is disabled.
−
DualFlash mode settings are invalid in any mode other than user mode.
1.3.7 Date buffer
This section explains the data buffer.
This series is equipped with data buffer of 128 bits × 2 in D-Code bus and DualFlash area.
1. D-Code bus data buffer
When the mode is CPU ROM mode (FASZR:ASZ="0b10") and FRWTR register RWT="0b10"/"0b11", D-Code bus data
buffer is enabled.
Up to 2 sets of data read from D-Code bus in the past is stored in 128-bit units. If the address hits in this buffer, it
becomes buffer hit and the value is output with 0 Wait.
In addition, FASZR register, FRWTR register, and DFCTRLR register is rewritten, the data stored in the data buffer is
cleared.
2. DualFlash data buffer
When the mode is DualFlash mode (DFCTRLR: DFE="1") with CPU ROM mode (DFASZR:DASZ="0b10") and
DFRWTR register DRWT="0b10"/"0b11", the data buffer in DualFlash area is enabled.
Up to 2 sets of data read from DualFlash area in the past is stored in 128-bit units. If the address hits in this buffer, it
becomes buffer hit and the value is output with 0 Wait.
In addition, DFASZR register, and DFRWTR register is rewritten, the data stored in the data buffer is cleared.
Notes:
−
For data buffer, data is stored in 128-bit units. Any data cannot be stored transcending the address boundary of 128-
bits.
−
Number of bits and columns of the Data buffer varies depending on each series of FM4. Number of CPU cycles is
different even if it is the same program depending on each series.
For detail, see
“Flash Programming Specifications” of each series.
