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MainFlash Memory

S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D

Figure 1-1 Memory Map of MainFlash Memory 1024 KB + 40 KB

Flash memory

1024KB

0x0000_0000

Security code

0x0040_0000

CR trimming data / HTM

0x0040_2000

0x0000_0000

SA4(#0) (8KB)

bit31

bit0

SA5(#0) (8KB)

SA8(#0) (32KB)

0x0000_4000

0x0001_0000

0x0002_0000

0x0004_0000

0x0006_0000

0x0008_0000

0x0010_0000

SA9(#0) (64KB)

SA6(#0) (8KB)

SA7(#0) (8KB)

SA10(#0) (64KB)

SA11(#0) (64KB)

SA12(#0) (64KB)

SA13(#0) (64KB)

SA14(#0) (64KB)

SA15(#0) (64KB)

0x0000_8000

SA16(#0) (64KB)

SA17(#0) (64KB)

SA18(#0) (64KB)

SA19(#0) (64KB)

0x000C_0000

0x000A_0000

SA20(#0) (64KB)

SA21(#0) (64KB)

SA22(#0) (64KB)

SA23(#0) (64KB)

0x000E_0000

0x0010_0000

0x000F_0000

0x000D_0000

0x000B_0000

0x0009_0000

0x0007_0000

0x0005_0000

0x0003_0000

0x0000_6000

0x0000_2000

General Purpose data

0x0040_4000

Flash memory

40KB

0x0040_6000

0x0041_0000

SA3(#0) (8KB)

SA0(#1) (8KB)

SA1(#1) (8KB)

SA3(#1) (8KB)

SA2(#1) (8KB)

0x0040_6000

0x0040_A000

0x0041_0000

0x0040_E000

0x0040_C000

0x0040_8000

Flash

Macro #0

Flash

Macro #1

Flash

Macro #0

Summary of Contents for S6E2C1 Series

Page 1: ...CC C5 C4 C3 C2 C1 Series 32 bit Microcontroller FM4 Family Flash Programming Specifications Document Number 002 04913 Rev D Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 www cypress...

Page 2: ...claim damage or other liability arising from any Security Breach In addition the products described in these materials may contain design defects or errors known as errata which may cause the product...

Page 3: ...nd operations of the flash security CHAPTER 3 Serial Programming Connection This chapter explains the basic configuration for serial write to flash memory by using the Cypress Serial Programmer Sample...

Page 4: ...Half word Indicates access in units of 16 bits Byte Indicates access in units of 8 bits Notations The notations in bit configuration of the register explanation of this document are written as follows...

Page 5: ...D 5 Contents 1 MainFlash Memory 6 1 1 Overview 7 1 2 Configuration 8 1 3 Operating Description 13 1 4 Registers 42 2 Flash Security 59 2 1 Overview 60 2 2 Operation Explanation 60 3 Serial Programmin...

Page 6: ...ins the structure operation and registers of the MainFlash memory This series has built in MainFlash memory with a capacity of 1064 KBytes to 2088 KBytes that supports data erasing by all sectors of e...

Page 7: ...tomatic algorithm 1 Because word access is not available programs that are contained in the flash memory cannot be executed while operating in this mode Half word access is available 3 ROM writer mode...

Page 8: ...d to the Flash Macro 0 Figure 1 1 to Figure 1 4 shows the address and sector structure of the MainFlash memory built into this series as well as the address of security CR trimming data HTM general pu...

Page 9: ...KB SA6 0 8KB SA7 0 8KB SA10 0 64KB SA11 0 64KB SA12 0 64KB SA13 0 64KB SA14 0 64KB SA15 0 64KB 0x0000_8000 SA16 0 64KB SA17 0 64KB SA18 0 64KB SA19 0 64KB 0x000C_0000 0x000A_0000 SA20 0 64KB SA21 0 64...

Page 10: ..._0000 0x000A_0000 SA20 0 64KB SA21 0 64KB SA22 0 64KB SA23 0 64KB 0x000E_0000 0x0010_0000 3 2 1 0 0x000F_0000 0x000D_0000 0x000B_0000 0x0009_0000 0x0007_0000 0x0005_0000 0x0003_0000 0x0000_6000 0x0000...

Page 11: ...0 0x000F_0000 0x000D_0000 0x000B_0000 0x0009_0000 0x0007_0000 0x0005_0000 0x0003_0000 0x0000_6000 0x0000_2000 General Purpose data 0x0040_4000 Flash memory 40KB 0x0040_6000 0x0041_0000 SA3 0 8KB SA0 1...

Page 12: ...ails on the HTM Table 1 2 shows the address of the HTM code area and the HTM code Table 1 2 Address of HTM Code and HTM Code Address HTM Code 0x0040_200C 0x0000_0001 CR trimming area CR Frequency trim...

Page 13: ...This section explains the MainFlash memory operation 1 3 1 MainFlash Memory Access Modes 1 3 2 Automatic Algorithm 1 3 3 Explanation of MainFlash Memory Operation 1 3 4 Writing to MainFlash Memory in...

Page 14: ...de is entered by setting the flash access size bits FASZR ASZ to 0b01 16 bit read write and enables flash programming Because word access is not possible in this mode programs that are contained in th...

Page 15: ...v D 15 1 3 2 Automatic Algorithm When CPU programming mode is used writing to and erasing MainFlash memory is performed by activating the automatic algorithm This section explains the automatic algori...

Page 16: ...any address within the address range of the target flash macro When the address outside the flash macro of flash address range is specified the command sequence would not operate correctly since the...

Page 17: ...tails on the actual operation Notes The command is not recognized properly if the fourth write command write data cycle is issued to an odd address Always issue it to an even address Only a single hal...

Page 18: ...tes Because writing and erasing of flash memory is performed by the automatic algorithm whether or not the automatic algorithm is currently executing can be checked using the flash ready bit FSTR RDY...

Page 19: ...t7 DPOL Data polling flag b When the hardware sequence flags are read by specifying an arbitrary address this bit uses a data polling function to indicate whether or not the automatic algorithm is cur...

Page 20: ...Reads out 0 When this bit is read out by specifying an address in the sector other than specified as sector erase Reads out the value of bit6 of a specified address While write is in progress When th...

Page 21: ...read by specifying an arbitrary address this bit indicates whether or not the flash memory is currently in the sector erase command timeout interval The value that is read out varies depending on the...

Page 22: ...checking the toggle operation of the read data During writing Reads out 0 During sector erase or flash erase When this bit is read out continuously 1 and 0 are alternately read toggle operation During...

Page 23: ...urned on there is no need to issue a data read command Furthermore because data can be read by normal read access and programs can be accessed by the CPU while in the read reset state there is no need...

Page 24: ...nly show the lower 12 bits The upper 20bits should be set to any address within the address range of the target flash memory When the address outside the flash address range is specified the command s...

Page 25: ...the hardware sequence flag Therefore if the value of bit7 the DPOL bit of the data that was read is 1 that means t the flash erase has finished The time required to erase the flash is sector erase ti...

Page 26: ...e the same Timing limit is exceeded TLOV bit Internal address read 1 Internal address read 2 TOGG bit values in Internal address read 1 and 2 are the same Flag for starting again from the remainder En...

Page 27: ...nd temporarily suspends the erase operation By sending the erase restart command the flash memory is returned to the sector erase state and can restart the suspended erase operation However even if th...

Page 28: ...n 1 3 2 Automatic Algorithm for details on the sector erase restart command Notes The sector erase restart command is only valid during sector erase suspended Even if the sector erase restart command...

Page 29: ...command Write address PA 2 Write data PD 31 16 At this time the hardware automatically calculates the ECC codes together with PD 15 0 from step 2 and also automatically writes the ECC codes at the sam...

Page 30: ...cifications of each series Flash Accelerator operating flow at RWT 0b10 in FRWTR register and the number of Wait are shown in Figure 1 9 Prefetch buffer access occurs at initial state If the address d...

Page 31: ...ent Number 002 04913 Rev D 31 Figure 1 9 Flash Accelerator Operating Flow FRWTR RWT 0b10 Trace Buffer read Prefetch Buffer read Prefetch enable Buffer hit buffer hit 1 cycle Buffer miss Prefetch hit 0...

Page 32: ...r mode and operate the prefetch buffer function but the trace buffer function has still been stopped In order to activate this function 1 must be written to BE bit in FBFCR Flash Buffer Control Regist...

Page 33: ...S6E2CC9 S6E2C1A S6E2C2A S6E2C3A S6E2C4A S6E2C5A S6E2CCA Dual flash mode DFCTRLR DFE 1 Setting is permitted Setting is permitted Setting is permitted Re Map function DFCTRLR RME 1 Setting is prohibite...

Page 34: ...64KB SA13 0 64KB SA14 0 64KB SA15 0 64KB 0x0000_8000 SA16 0 64KB SA17 0 64KB SA18 0 64KB SA19 0 64KB 0x000C_0000 0x000A_0000 SA20 0 64KB SA21 0 64KB SA22 0 64KB SA23 0 64KB 0x000E_0000 0x0010_0000 3 2...

Page 35: ...0 64KB SA23 0 64KB 0x000E_0000 0x0010_0000 3 2 1 0 0x000F_0000 0x000D_0000 0x000B_0000 0x0009_0000 0x0007_0000 0x0005_0000 0x0003_0000 0x0000_6000 0x0000_2000 General Purpose data 0x0040_4000 Flash me...

Page 36: ...09_0000 0x0007_0000 0x0005_0000 0x0003_0000 0x0000_6000 0x0000_2000 General Purpose data 0x0040_4000 Flash memory 8KB 0x0040_6000 0x0041_0000 SA3 0 8KB 0x0040_6000 0x0040_8000 Flash Macro 0 Flash Macr...

Page 37: ...0x000C_0000 0x000A_0000 SA20 1 64KB SA21 1 64KB SA22 1 64KB SA23 1 64KB 0x000E_0000 0x0010_0000 3 2 1 0 0x000F_0000 0x000D_0000 0x000B_0000 0x0009_0000 0x0007_0000 0x0005_0000 0x0003_0000 0x0000_6000...

Page 38: ...ral purpose data is assigned to the DualFlash area Be careful not to accidentally perform deleting or writing CR trimming area CR Frequency trimming data 0x200F_8000 bit31 bit0 3 2 1 0 Security code a...

Page 39: ...sing of data This mode is entered by setting the dual flash access size bits DFASZR DASZ to 0b01 16 bit read write and enables flash programming Because word access is not possible in this mode progra...

Page 40: ...ngs are invalid in any mode other than user mode 1 3 7 Date buffer This section explains the data buffer This series is equipped with data buffer of 128 bits 2 in D Code bus and DualFlash area 1 D Cod...

Page 41: ...ister FASZR do not transition to low power consumption mode If the CPU ROM mode is configured ASZ 0b10 in the ASZ 1 0 bits of the flash access size register FASZR do not write to the flash memory If t...

Page 42: ...Register 1 4 17 DFSTR Flash Status Register 1 4 18 1 4 1 FASZR Flash Access Size Register This section explains the FASZR This register configures the access size for flash memory except DualFlash ar...

Page 43: ...used when HCLK is over 72 MHz 11 Flash Accelerator mode 1 Initial value This setting must be used when HCLK is over 160 MHz In flash accelerator mode allowing operating Flash Accelerator prefetch buf...

Page 44: ...ed See bit5 TLOV Timing Limit Exceeded Flag Bit If this bit becomes 1 issue a reset command See Section 1 3 2 1 Command Sequence Because the correct value might not be read out immediately after issui...

Page 45: ...d values are undefined Ignored on write bit2 0 SD Sync Down The wait cycle is inserted in the lead access of the flash memory Field bit Description SD 2 0 000 0 Initial value 001 1 Wait 010 Setting is...

Page 46: ...Status 0 Trace buffer function is in stop or in initializing 1 Trace buffer function operation is allowed bit0 BE Buffer Enable Field bit Description BE 0 Buffer Enable 0 Trace buffer function will be...

Page 47: ...CPU is generated Field bit Description ERRIE 2 Flash ECC Error Interrupt Enable 0 ECC error correction interrupt is disabled Initial value 1 ECC error correction interrupt is enabled bit1 HNGIE Flash...

Page 48: ...RC bit of FICLR register Field bit Description ERRIF 2 Flash ECC Error Interrupt Flag 0 The generation of ECC error correction is not detected 1 The generation of ECC error correction is detected bit1...

Page 49: ...sh ECC Error Interrupt Clear At write 0 ECC error correction interrupt flag ERRIF is not changed 1 ECC error correction interrupt flag ERRIF is cleared At read 0 is read out bit1 HNGIC Flash HANG Inte...

Page 50: ...eld bit Description RME 1 Re Map Enable 0 Flash Macro 1 is assigned to DualFlash area Initial value 1 Flash Macro 0 is assigned to DualFlash area bit1 DFE Dual Flash mode Enable This bit set the dual...

Page 51: ...of the FM4 Family Peripheral Manual for details on the CR temperature trimming data Field bit Description TTRMM 20 16 Reads out bit 4 0 of an address of 0x0040_2002 bit15 10 Reserved bits The read va...

Page 52: ...se Data1 After reset is released store the bit 31 0 in an address of 0x0040_4000 general purpose data1 of the flash memory area into this register Field bit Description GPD1 31 0 Reads out bit 31 0 of...

Page 53: ...se Data2 After reset is released store the bit 31 0 in an address of 0x0040_4004 general purpose data2 of the flash memory area into this register Field bit Description GPD2 31 0 Reads out bit 31 0 of...

Page 54: ...se Data3 After reset is released store the bit 31 0 in an address of 0x0040_4008 general purpose data3 of the flash memory area into this register Field bit Description GPD3 31 0 Reads out bit 31 0 of...

Page 55: ...the general purpose data4 stored in the register on the RAM etc When Re Map function is enabled this value does not change 1 4 15 FERRAD Flash ECC ERR Address Capture Register This section explains FE...

Page 56: ...ze Specifies the access size of the flash memory Field bit Description DASZ 1 0 Dual Flash Access Size 00 Setting prohibited 01 16 bit read write CPU programming mode 10 32 bit read CPU ROM mode Initi...

Page 57: ...his setting can be used when HCLK is 72 MHz or less 01 Setting prohibited 10 4 cycles wait mode This setting can be used when HCLK is 160MHz or less This setting must be used when HCLK is over 72 MHz...

Page 58: ...command See Section 1 3 2 1 Command Sequence Because the correct value might not be read out immediately after issuing an automatic algorithm command ignore the value of this bit as read out the firs...

Page 59: ...Specification Document Number 002 04913 Rev D 59 2 Flash Security The flash security function protects contents of the MainFlash memory This section describes the overview and operations of the flash...

Page 60: ...flash erase command to the Flash Macro 1 of MainFlash memory 2 Confirm if the flash erase operation for the Flash Macro 1 of MainFlash memory is completed 3 Issue the flash erase command to the Flash...

Page 61: ...umber 002 04913 Rev D 61 3 Serial Programming Connection This series supports serial onboard write Cypress standard to flash memory This chapter explains the basic configuration for serial write to fl...

Page 62: ...g tool for all microcontrollers with built in flash memory Two types of Serial Programmer are available according to the PC interface RS 232C or USB used Choose the type according to your environment...

Page 63: ...illator or external clock or built in High speed CR oscillator If flash erase is executed to the flash memory that its flash security is enabled when built in CR oscillator is used instead of external...

Page 64: ...cillation clock When crystal oscillator is used the communication will start with a baud rate of 115200 bps Table 3 2 shows available frequencies and communication baud rates at start up Figure 3 2 Co...

Page 65: ...clock oscillation may be unstable When the X1 pin cannot be opened please use built in high speed CR oscillator for reliable communication Figure 3 3 Connection Example When External Clock is Used Ta...

Page 66: ...built in high speed CR oscillator would fluctuate due to temperature and voltage change the allowable baud rate error range might be exceeded For using the built in high speed CR oscillator see Built...

Page 67: ...nected through a USB cable Figure 3 5 shows the basic configuration of FLASH USB DIRECT Programmer and Table 3 3 lists the system configuration Figure 3 5 Basic Configuration of FLASH USB DIRECT Progr...

Page 68: ...a connection example when VCC 3 3V Insert a level shifter for each system The pull up and pull down resistance values shown are for example Select the most appropriate resistance values for each syste...

Page 69: ...r 3 3V output USB connector Vbus D D GND UDM0 UDP0 VSS P60 USBVCC VCC INITX P61 UHCONX Note The pull up and pull down resistance values shown are for example Select the most appropriate resistance val...

Page 70: ...he start of communication enables the clock asynchronous communication mode and setting it to L enables the clock synchronous communication mode When the communication mode is set to UART this pin can...

Page 71: ...ange Description of Change 09 30 2014 AKIH Initial release A 04 25 2016 AKIH Migrated to Cypress format B 06 09 2017 YSAT Adapted Cypress new logo C 10 24 2017 NOSU Add a note about address notation i...

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