Cypress S6E2C1 Series, Manual

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MainFlash Memory
S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D 30
1.3.5 MainFlash Accelerator
This section explains the MainFlash accelerator.
This series is equipped with Flash accelerator for instruction code to achieve 0 wait at high speed operation (MAX: 200
MHz).
The Flash accelerator has the following functions:
1. Prefetch Buffer
Addresses will be prefetched to save the instructions in the prefetch buffer. The prefetch buffer consists of 128 bits × 4.
If the address hits in this buffer, the value will be output with 0 Wait.
2. Trace Buffer
16 Kbyte RAM is employed for trace buffer. Values read from the Flash memory will be stored in this buffer at all times.
After instruction fetch, if the value has been stored in the trace buffer, it becomes buffer hit and output the value with 0
Wait.
Notes:
−
Number of bits and columns of the prefetch buffer varies depending on each series of FM4. Number of CPU cycles
is different even if it is the same program depending on each series.
For detail, see
“Flash Programming Specifications” of each series.
Flash Accelerator operating flow at RWT=
”0b10” in FRWTR register and the number of Wait are shown in
Figure 1-9 .
Prefetch buffer access occurs at initial state. If the address do not hit in the prefetch buffer, it becomes prefetch miss.
Then, it waits for one cycle and the access is switched to the trace buffer. However, if the value is hit in the trace buffer, it
becomes buffer hit and outputs the value stored in the trace buffer with 0 Wait.
If the address do not hut in the trace buffer and a buffer miss occurs, the access will be switched to one for prefetch buffer
again. In that time, the access to the flash memory occurs and the wait cycle of 4 or 5 cycle wait is generated.
If the address do not hit in both prefetch buffer and trace buffer, 3 or 4 cycle wait for flash memory access is generated.
When the trace buffer function is disabled by register setting (See Section " 1.4.5 FBFCR (Flash Buffer Control Register) "),
switch from prefetch buffer to trace buffer does not occur. At the prefetch miss, it requires 3 or 4 cycle wait cycle for flash
memory access.
Flash Accelerator operating flow at RWT=
”0b11” in FRWTR register and the number of Wait are shown in
Figure 1-10 .
The number of Wait is different from RWT=
”0b10” in FRWTR register.