S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
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1.4.4 FSYNDN (Flash Sync Down Register)
This section explains the FSYNDN.
The wait cycle is inserted in the read access to the flash memory at the CPU ROM mode. Current consumption can be
reduced by decreasing the access clock frequency of the flash memory.
bit
7
6
5
4
3
2
1
0
Field
Reserved
SD
Attribute
RW
RW
RW
Initial Value
0
0
0
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2:0] SD: Sync Down
The wait cycle is inserted in the lead access of the flash memory.
Field
bit
Description
SD
2:0
000: 0(Initial value)
001: +1 Wait
010: Setting is prohibited.
011: +3 Wait
100: Setting is prohibited.
101: +5 Wait
110: Setting is prohibited.
111: +7 Wait
The number of wait set by this bit is added to the RWT bits of the flash read wait register (FRWTR).
Example)
RWT=”0b00” (0cycle wait and SD=”0b011”, 0+3=3 wait
Notes:
−
This register is valid only when RWT bits in FRWTR register is set to "00". In Flash Accelerator mode
(RWT=”0b10”/RWT=”0b11”), the value of this register is ignored.
−
Perform a dummy read to register, after changing this register.
