CYW954907AEVAL1F Evaluation Kit User Guide, Doc. No. 002-22338 Rev. **
29
4.
Hardware
This chapter describes the CYW954907AEVAL1F EVK hardware and its different blocks, such as
Bootstrap, reset control, Arduino-compatible headers, and module connectors.
The schematic is available at the following location after installing the software from
Software Instal-
lation
.
<WICED_SDK_Directory>\43xx_Wifi\platforms\CYW954907AEVAL1F\schematics.
4.1
Bootstrap
Bootstrap options available in the CYW954907AEVAL1F EVK are shown in
Table 4-1
. The pins are
sampled at power-on reset (POR) to determine various operating modes. Sampling occurs a few
milliseconds after an internal POR or de- assertion of the external POR. After the POR, each pin
assumes the GPIO or alternative function specified in CYW54907 Alternate GPIO function table in
the CYW54907 Datasheet s(002-19312).
Care should be taken to ensure SPI mode and SDIO Host are not turned on at the same time since
they share the same set of lines. For more information regarding bootstrap options, refer to the
CYW54907 Datasheet (002-19312).
Bootstrap options other than GPIO_7 and GPIO_13, are not available for the user to modify in this
board.
To change Bootstrap options for GPIO_7 and GPIO_13, refer the "Bootstraps, Flash" page of sche-
matics.
Table 4-1. Bootstrap Options Available in CYW954907AEVAL1F EVK
Pin
Strp Function
Strap Pull
Chip default
Board Default
GPIO_1
gSPI Mode
0 = Enable gSPI Mode
1 = Disable gSPI Mode
0
0
GPIO_7
WCPU Boot Mode:
0 = TCROM Boot
1 = TCMSRAM Boot
0
1
R135=10K to
WLAN_VDDIO
GPIO_11
ACPU Boot Mode:
0 = SOCROM Boot
1 = SOCSRAM Boot
0
0