Appendix
CY8CKIT-044 PSoC® 4 M-Series Pioneer Kit Guide, Doc. No. 001-96598 Rev. *C
57
A.4.
Using FM24V10 F-RAM
This chapter describes advanced features of the PSoC 4 M-Series Pioneer Kit as well as the corresponding projects. It can
be used as a reference to exploit these features for other applications, according to the needs of the project.
The PSoC 4 M-Series Pioneer board has an onboard ferroelectric RAM chip that can hold up to 1 Mb of data. The chip
provides an I2C communication interface for data access. It is hardwired to the I2C interface (P4[0] and P4[1] of the PSoC 4
M-Series); the same lines are routed to the PSoC 5LP I2C interface. Because the F-RAM device is an I2C slave, it can be
accessed or shared among various I2C masters on the same lines. For more details on the F-RAM device, refer to the
device
datasheet
.
A.4.1 Address Selection
The slave address of the F-RAM device consists of three parts, as shown in
Figure A-15:
slave ID, device select, and page
select. Slave ID is an F-RAM family-specific ID provided in the datasheet of the particular F-RAM device. For the device
used on the PSoC 4 M-Series Pioneer board (FM24V10), the slave ID is 1010b. Device select bits are set using the two
physical pins A2 and A1 in the device. The setting of these two pins in PSoC 4 M-Series Pioneer board is controlled by
resistors R21/R20 (A1) and R23/R22 (A2). Because the memory location in F-RAM is divided into two pages of 64 KB each,
the page select bit is used to refer to one of the two pages in which the read or write operations will take place.
Figure A-25. F-RAM I2C Address Byte Structure
A.4.2 Write/Read Operation
The F-RAM device datasheet includes details on how to perform a write/read operation with the F-RAM.
Figure A-26
and
Figure A-27
provide a snapshot of the write/read packet structure as a quick reference.
Figure A-26. F-RAM Single-Byte and Multiple-Byte Write Packet Structure
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