Appendix
CY8CKIT-044 PSoC® 4 M-Series Pioneer Kit Guide, Doc. No. 001-96598 Rev. *C
58
Figure A-27. F-RAM Single-Byte and Multiple-Byte Read Packet Structure
As the figures show, operations start with the slave address followed by the memory address. For write operations, the bus
master sends the slave address and memory address followed by one or more data bytes. Each byte of data is written to
consecutive locations in the memory, and the memory generates an acknowledgement condition.
For ‘Current Address Read’ and ‘Sequential Read’, the bus master sends only the slave address. The memory address
used
is the same address that was set by the previous ‘Write’ or ‘Selective Read’ operation. For ‘Selective Read’
operations, after receiving the complete slave address and memory address, the memory will begin shifting data from the
current address on the next clock
Note:
The example project Sensor Hub uses the onboard F-RAM. See the
Sensor Hub
project to understand how to
communicate with the F-RAM device using PSoC 4200M device. You can also communicate with the F-RAM using the
Bridge Control Panel (BCP) software similar to the way you communicate with any other I2C slave device. Refer to the
KitProg User Guide
for more details on how to use the BCP to communicate with an I2C slave device.
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