PSoC® 4100S Pioneer Kit Guide, Doc. # 002-14067 Rev. *C
21
Kit Operation
❐
48-MHz ARM
®
Cortex
®
-M0+ CPU
❐
Up to 64KB flash, 8KB SRAM
❐
Real-time clock capability with a WCO
■
Programmable Analog Blocks
❐
One 12-bit, 1-Msps SAR ADC
❐
One 10-bit, 46.8-Ksps Single-Slope ADC
❐
Two opamps configurable as PGAs, comparators, etc.
❐
Two low-power comparators (CMP)
❐
One CapSense
®
block that supports low-power operation with self- and mutual-capacitance
sensing
❐
Two 7-bit IDACs configurable as a single 8-bit IDAC
■
Programmable Digital Blocks
❐
Five 16-bit Timer, Counter, PWM (TCPWM) blocks
❐
Three serial communication blocks (SCBs) that are configurable as I2C, SPI or UART
■
Packages
❐
35-ball WLCSP, 32-pin QFN, 40-pin QFN, 48-pin TQFPUp to 36 GPIOs, including
16 Smart I/Os
Refer to the
PSoC 4100S datasheet
for more details on the device features.
Figure 3-2
shows the block diagram for the PSoC 4100S Pioneer Kit.
Figure 3-2. Block Diagram of PSoC 4100S Pioneer Kit
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