Cypress CY8C28 series, Technical Reference Manual

Page: 390 / 571

CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G 389
Analog Register Summary
The following table lists all the PSoC registers for the analog system in address order (Add. column) within their system
resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written
with a value of ‘0’. The naming conventions for the SC and CT registers and their arrays of PSoC blocks are detailed in their
respective table title rows.
Note that all PSoC devices, with a base part number of CY8C28xxx fall into one of the following categories with respect to
their analog PSoC arrays: 4 column device, 2 column device, or 0 column device. The “PSoC Analog System Block Diagram”
at the beginning of this section illustrates this.
In the following table, the third column from the left titled “Analog Columns” indicates which of the three PSoC device catego-
ries the register falls into. To determine the number of analog columns in your PSoC device, refer to the table titled
“PSoC
Device Characteristics” on page 387 .
Summary Table of the Analog Registers
Add. Name
Analog
Cols.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
ANALOG INTERFACE REGISTERS (page 400 )
0,62h CLK_CR3 4 SYSDIR[3:0] RW : 00
0,64h CMP_CR0
4 COMP[3:0] AINT[3:0]
# : 00
2 COMP[1:0] AINT[1:0]
0,65h ASY_CR 4, 2 SARCNT[2:0] SARSIGN SARCOL[1:0] SYNCEN RW : 00
0,66h CMP_CR1
4 CLDIS[3] CLDIS[2] CLDIS[1] CLDIS[0]
RW : 00
2 CLDIS[1] CLDIS[0] CLK1X[1] CLK1X[0]
0,E6h DEC_CR0 4, 2 IGEN[3:0] ICLKS0 DCOL[1:0] DCLKS0 RW : 00
0,E7h DEC_CR1
4 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1
RW : 00
2 ECNT IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1
1,60h CLK_CR0
4 AColumn3[1:0] AColumn2[1:0] AColumn1[1:0] AColumn0[1:0]
RW : 00
2 AColumn1[1:0] AColumn0[1:0]
1,61h CLK_CR1 4, 2 SHDIS ACLK1[2:0] ACLK0[2:0] RW : 00
1,63h AMD_CR0
4 AMOD2[2:0] AMOD0[2:0]
RW : 00
2 AMOD0[2:0]
1,64h CMP_GO_EN 2 GOO5 GOO1 SEL1[1:0] GOO4 GOO0 SEL0[1:0] RW : 00
1,65h CMP_GO_EN1 2 GOO7 GOO3 SEL3[1:0] GOO6 GOO2 SEL2[1:0] RW : 00
1,66h AMD_CR1
4 AMOD3[2:0] AMOD1[2:0]
RW : 00
2 AMOD1[2:0]
1,67h ALT_CR0 4, 2 LUT1[3:0] LUT0[3:0] RW : 00
1,68h ALT_CR1 4 LUT3[3:0] LUT2[3:0] RW : 00
1,69h CLK_CR2 4 ACLK1R ACLK0R RW : 00
ANALOG INPUT CONFIGURATION REGISTERS (page 419 )
0,60h AMX_IN
4 ACI3[1:0] ACI2[1:0] ACI1[1:0] ACI0[1:0]
RW : 00
2 ACI1[1:0] ACI0[1:0]
1,62h ABF_CR0
4 ACol1Mux ACol2Mux ABUF1EN ABUF2EN ABUF0EN ABUF3EN Bypass PWR
RW : 00
2 ACol1Mux ABUF1EN ABUF0EN Bypass PWR
1,6Ah AMUX_CFG1 ABusMux3 ABusMux2 ACol3Mux ACol0Mux MUXCLKR[2:0] ENR RW : 00
ANALOG REFERENCE REGISTER (page 421 )
0,63h ARF_CR 4, 2 HBE REF[2:0] PWR[2:0] RW : 00
CONTINUOUS TIME PSoC BLOCK REGISTERS (page 426 )
0,70h ACC00CR3 4, 2 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00
0,71h ACC00CR0 4, 2 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00
0,72h ACC00CR1 4, 2 AnalogBus CompBus NMux[2:0] PMux[2:0] RW : 00
0,73h ACC00CR2 4, 2 CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] RW : 00