CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
151
CMP_CR1
0,66h
13.2.24
CMP_CR1
Analog Comparator Bus Control Register 1
This register is used to override the analog column comparator synchronization, or select direct column clock
synchronization.
By default, the analog comparator bus is synchronized by the column clock and driven to the digital comparator bus for use in
the digital array and the interrupt controller. The CLDIS bits are used to bypass the synchronization. This bypass mode can be
used in power down operation to wake the device out of sleep, as a result of an analog column interrupt. Most devices update
the comparator bus on the rising edge of PHI2. The CY8C28xxx PSoC devices have the option to synchronize using PHI2 or,
when the CLK1X bits are set for a given column, 1X rising edge column clock sync is enabled. For additional information,
“Register Definitions” on page 400
in the Analog Interface chapter.
7
CLDIS[3]
Controls the comparator output latch, column 3.
0
Comparator bus synchronization is enabled.
1
Comparator bus synchronization is disabled.
6
CLDIS[2]
Controls the comparator output latch, column 2.
0
Comparator bus synchronization is enabled.
1
Comparator bus synchronization is disabled.
5
CLDIS[1]
Controls the comparator output latch, column 1.
0
Comparator bus synchronization is enabled.
1
Comparator bus synchronization is disabled.
4
CLDIS[0]
Controls the comparator output latch, column 0.
0
Comparator bus synchronization is enabled.
1
Comparator bus synchronization is disabled.
3
CLK1X[3]
Controls the digital comparator bus 3 synchronization clock.
0
Comparator bit is synchronized by rising edge of PHI2.
1
Comparator bit is synchronized directly by selected column clock. (This clock is not divided
by 4.)
2
CLK1X[2]
Controls the digital comparator bus 2 synchronization clock.
0
Comparator bit is synchronized by rising edge of PHI2.
1
Comparator bit is synchronized directly by selected column clock. (This clock is not divided
by 4.)
1
CLK1X[1]
Controls the digital comparator bus 1 synchronization clock.
0
Comparator bit is synchronized by rising edge of PHI2.
1
Comparator bit is synchronized directly by selected column clock. (This clock is not divided
by 4.)
(continued on next page)
Individual Register Names and Addresses:
0,66h
CMP_CR1: 0,66h
4 COLUMN
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
CLDIS[3]
CLDIS[2]
CLDIS[1]
CLDIS[0]
CLK1X[3]
CLK1X[2]
CLK1X[1]
CLK1X[0]
Bits
Name
Description
Summary of Contents for CY8C28 series
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