CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
147
CLK_CR3
0,62h
13.2.20
CLK_CR3
Analog Clock Source Control Register 3
The Analog Clock Source Control Register 3 (CLK_CR3) is used to select the clock source for an individual analog column.
In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits
should always be written with a value of ‘0’. For additional information,
see “Register Definitions” on page 400
in the Analog
Interface chapter.
3:0
SYSDIR[3:0]
0
Associated ACC column's clock source is determined by setting of CLK_CR0.
1
Associated ACC column's clock source is SYSCLK.
Individual Register Names and Addresses:
0,62h
CLK_CR3: 0,62h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
Bit Name
SYSDIR[3:0]
Bits
Name
Description
Summary of Contents for CY8C28 series
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