CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
149
CMP_CR0
0,64h
13.2.22
CMP_CR0
Analog Comparator Bus Control Register 0
This register is used to poll the analog column comparator bus states and select column interrupts. For additional information,
see “Register Definitions” on page 400
in the Analog Interface chapter.
7
COMP[3]
Comparator bus state for column 3.
This bit is updated on the
latch disable bits are set (refer to the
CLDISx bits in the
register). If the comparator latch disable bits are set, then this bit is transparent
to the comparator bus in the analog array.
6
COMP[2]
Comparator bus state for column 2.
This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the
register). If the comparator latch disable bits are set, then this bit is transpar-
ent to the comparator bus in the analog array.
5
COMP[1]
Comparator bus state for column 1.
This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the
CLDISx bits in the
register). If the comparator latch disable bits are set, then this bit is transpar-
ent to the comparator bus in the analog array.
4
COMP[0]
Comparator bus state for column 0.
This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the
CLDISx bits in the
register). If the comparator latch disable bits are set, then this bit is transparent
to the comparator bus in the analog array.
3
AINT[3]
Controls the selection of the analog comparator interrupt for column 3.
0
The comparator data bit from the column is the input to the interrupt controller.
1
The
of PHI2 for the column is the input to the interrupt controller.
2
AINT[2]
Controls the selection of the analog comparator interrupt for column 2.
0
The comparator data bit from the column is the input to the interrupt controller.
1
The falling edge of PHI2 for the column is the input to the interrupt controller.
1
AINT[1]
Controls the selection of the analog comparator interrupt for column 1.
0
The comparator data bit from the column is the input to the interrupt controller.
1
The falling edge of PHI2 for the column is the input to the interrupt controller.
In 2 column limited analog PSoC devices, this bit selects the terminal count for the dedicated incremental
PWM as the interrupt source.
0
AINT[0]
Controls the selection of the analog comparator interrupt for column 0.
0
The comparator data bit from the column is the input to the interrupt controller.
1
The falling edge of PHI2 for the column is the input to the interrupt controller.
In 2 column limited analog PSoC devices, this bit selects the terminal count for the dedicated incremental
PWM as the interrupt source.
Individual Register Names and Addresses:
0,64h
CMP_CR0: 0,64h
7
6
5
4
3
2
1
0
Access : POR
R : 0
RW : 0
Bit Name
COMP[3:0]
AINT[3:0]
Bits
Name
Description
Summary of Contents for CY8C28 series
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