CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
237
CLK_CR1
1,61h
13.3.17
CLK_CR1
Analog Clock Source Control Register 1
This register is used to select the clock source for an individual analog column.
There are two ranges of Digital PSoC blocks shown. The range is set by bits ACLK0R and ACLK1R in register
the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits
should always be written with a value of ‘0’. For additional information, refer to the
“Register Definitions” on page 400
in the
Analog Interface chapter.
6
SHDIS
Sample and hold disable.
0
Enabled
1
Disabled
5:3
ACLK1[2:0]
Select the clocking source for Analog Clock 1.
000b
Digital Basic Block 00 or 20
001b
Digital Basic Block 01 or 21
010b
Digital Communication Block 02 or 22
011b
Digital Communication Block 03 or 23
100b
Digital Basic Block 10
101b
Digital Basic Block 11
110b
Digital Communication Block 12
111b
Digital Communication Block 13
Note
Selection determined by setting of ACLK1R.
2:0
ACLK0[2:0]
Select the clocking source for Analog Clock 0.
000b
Digital Basic Block 00 or 20
001b
Digital Basic Block 01 or 21
010b
Digital Communication Block 02 or 22
011b
Digital Communication Block 03 or 23
100b
Digital Basic Block 10
101b
Digital Basic Block 11
110b
Digital Communication Block 12
111b
Digital Communication Block 13
Note
Selection determined by setting of ACLK1R.
Individual Register Names and Addresses:
1,61h
CLK_CR1: 1,61h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
Bit Name
SHDIS
ACLK1[2:0]
ACLK0[2:0]
Bits
Name
Description
Summary of Contents for CY8C28 series
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