Cypress Semiconductor CY8CKIT-015, Manual

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CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. ** 3
Contents
1. Introduction 5
1.1 Overview......................................................................................................................5
1.2 Prerequisites................................................................................................................5
1.3 Features.......................................................................................................................5
1.4 Kit Contents .................................................................................................................6
1.5 Development Kit Compatibility.....................................................................................6
1.6 Document History ........................................................................................................6
1.7 Documentation Conventions .......................................................................................6
2. Getting Started 7
2.1 Software Installation ....................................................................................................7
2.2 Hardware Setup...........................................................................................................8
3. Example Project 11
3.1 Running the Example Firmware ................................................................................11
3.2 Example Project - Overview ......................................................................................12
3.3 PSoC 1 Power Supervisor Solution ...........................................................................14
3.4 Technical Details .......................................................................................................15
3.4.1 Voltage Sequencing .......................................................................................15
3.4.2 UV and OV Monitoring using Window Comparator........................................17
3.4.3 Voltage and Current Measurements ..............................................................19
3.4.4 Regulator Trimming and Margining ................................................................19
3.4.5 Other Features ...............................................................................................20
3.4.6 Firmware Flowchart........................................................................................20
3.4.7 PSoC 1 Resource Usage Details ...................................................................23
A. Appendix 25
A.1 PSoC Power Supervision EBK Hardware Overview..................................................25
A.1.1 2x20 Pin Interface Header .............................................................................26
A.1.2 EBK Headers and Jumpers............................................................................27
A.2 CY8CKIT-035 Schematics.........................................................................................28
A.2.1 Primary 12-V Power Input ..............................................................................28
A.2.2 DVK Connector and Debug Test Points.........................................................28
A.2.3 Voltage Regulator V1 = 5 V ...........................................................................29
A.2.4 Voltage Regulator V2 = 3.3 V ........................................................................29
A.2.5 Voltage Regulator V3 = 2.5 V ........................................................................29
A.2.6 Voltage Regulator V4 = 1.8 V ........................................................................30
A.2.7 I2C/SMBus/PMBus Interface Connector........................................................30
A.3 CY8CKIT-035 Board Layout ......................................................................................31
A.3.1 Top layer ........................................................................................................31
A.3.2 Ground Layer .................................................................................................31
A.3.3 Power Layer ...................................................................................................32