Cypress Semiconductor CY8CKIT-015, Manual

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CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. ** 25
A. Appendix
A.1 PSoC Power Supervision EBK Hardware Overview
Figure 0-1. EBK Hardware Components
The Power Supervision EBK board consists of a 12-V primary input power source and four second-
ary voltage rails: V1 = 5 V, V2 = 3.3 V, V3 = 2.5 V, and V4 = 1.8 V. Voltage rail V1 feeds power to the
other three rails V2, V3, and V4. Therefore, disabling V1 will disable V2 to V4. Each secondary rail
consists of a regulator with enable input, circuitry that enables PSoC 1 to apply a DC control voltage
to the regulator feedback or adjust pin, as well as fixed and adjustable (potentiometer) load ele-
ments. Two jumpers are provided for each rail to disconnect all loads or disconnect only the adjust-
able load.
The EBK provides an I2C/SMBus/PMBus connector. A 40-pin (2×20) header J1 is provided to con-
nect this board with the host PSoC 1 on a development kit platform, such as the CY8CKIT-001 PSoC
DVK. The header carries voltage enables, regulator voltage, regulator load currents, and trim/margin
control signals for each regulator on the EBK. The I2C physical layer signals (SDA/SCL) from the
PSoC 1 are also routed across this header to allow connection to an external host or management
processor that supports standard I2C, SMBus, or PMBus protocol interfaces.