Cypress Semiconductor CY8CKIT-015, Manual

Page: 19 / 36

CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. ** 19
Example Project
3.4.3 Voltage and Current Measurements
Voltage monitoring in a power supervision system is measuring all of the rail voltages. The mea-
sured rail voltages can be used for trimming and to regulate the power consumption based on the
load connected to the rail. Also, the voltages can be communicated to the host so that it can log the
information.
A dedicated 10-bit SAR ADC is used to measure voltages of four rails on the CY8CKIT-035. The four
rail voltages from EBK are multiplexed to the same SAR ADC. The reference for ADC is derived
from the on-chip reference generator multiplex (RefMux) and the conversion range is selected as
0 V to 4.16 V. Both the 5-V rail and 12-V power rail are scaled down to within the ADC range.
Because the measured voltage is used for trimming, the voltage measurement and trimming are
inter-related and occur sequentially.
4+1 current monitoring uses two 14-bit delta-sigma ADCs. The currents delivered by 12-V and 5-V
rail are measured by one of those ADCs in a single-ended mode along with a unity gain buffer. Both
these rails have an high-side current sense amplifier each on the EBK to provide single-ended signal
for current measurement. The currents delivered by 3.3-V, 2.5-V, and 1.8-V rails are measured using
the other delta-sigma ADC along with an instrumentation amplifier. These rails have series sense
resistors on high sides on EBK. The instrumentation amplifier converts the differential signal across
the sense resistor to single-ended signal. The two ADCs are used because of the different input
ranges, which cannot be accommodated with a single ADC. The delta-sigma ADCs works with the
same reference voltage as that of SAR ADC.
At the time of multiplexing, after the input to the ADC is changed, three samples of digital data must
be discarded. This is required because the delta-sigma ADC works by oversampling the input and
decimating the single-bit results. Because all output data is dependent on analog input over a period
of time, the conversions that happen after changing the input will be invalid.
3.4.4 Regulator Trimming and Margining
To trim (fine tune) each regulator output, apply a controlled analog voltage to the "feedback" (VFB) or
"adjust" (VADJ) analog control pin on the regulators. To support trimming on the four secondary
power supply rails, four additional DACs to the ones already being used are required for the UV or
OV window comparator circuit. As the number of regulators in the system expands, the number of
DACs required for trimming and margining becomes excessive. To make more efficient use of ana-
log hardware resources, an alternative implementation is developed based on PWM blocks with
external RC filter networks to achieve the equivalent result. Because PSoC can measure the analog
voltage of each rail, a closed loop control system can be implemented to fine tune each regulator
output beyond the accuracy specifications of the regulators themselves.
The circuit in Figure 3-10 shows the detail of the trimming and margining circuit for the V3=2.5-V rail.
The output scaling network of R46 and R51 are the recommended values provided by the regulator
manufacturer to ensure that the regulator can sense its own output voltage and regulate it as the
load varies. The TR3 pin is a PWM output signal from PSoC that is filtered by R54/C15; that voltage
is summed into the FB pin of the regulator through R50.
If the PWM duty cycle controlled by PSoC 1 is reduced, the voltage applied to the FB will reduce and
the regulator will respond by increasing its output voltage. Conversely, if the PWM duty cycle is
increased, the voltage applied to the FB pin will increase and the regulator will respond by decreas-
ing its output voltage. Typical power supplies respond in this manner; for others that do not, this cir-
cuit both internal to PSoC 1 and external can be customized for the specific power supply chosen
(for example, inverting the PWM output such that a decrease in PWM duty cycle decreases the reg-
ulator output voltage).