Cypress Semiconductor CY8CKIT-015, Manual

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16 CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. **
Example Project
■
A Power Good (PGOOD) signal that indicates the correctness of the voltage on a particular rail.
The PGOOD signal can be generated by either the regulator or the controller. Currently, it is gen-
erated by PSoC 1 using a window comparator. The window comparator is explained in detail in
the next section.
When a sequencing fails, all the regulators will be disabled simultaneously. An error message along
with the rail number that is faulty is displayed on the LCD. With some modifications to the firmware,
you can easily implement power-down sequencing in different orders when a power fail occurs.
Figure 3-8. Voltage Sequencer Flowchart
The voltage sequencing algorithm works depending on the following parameters:
■
Sequencing Mode: This indicates the sequencing order in which the four rails must be powered
up. Six different modes are available.
■
Ramp Delay: This indicates the time that the sequencer must wait before monitoring the rail for its
goodness (checking the PGOOD) after the regulator is enabled.
■
Slot Delay: This indicates the time that the sequencer must wait before sequencing the next rail
after the current rail is verified with the correct voltage (PGOOD = 1).
To change the behavior of the voltage sequencer, change the parameters for the sequencer. To do
this, open the
configuration.h
file of the project in PSoC Designer 5.2 SP1. Change the definition of
DEFAULT_SEQUENCING_MODE by choosing any of the defined sequencing modes from
Start
Start Window Comparator block for
generating PGOOD signal
Start Delay Counter to generate
sequencing delays
Enable Regulator n
Execute Ramp delay for rail n
PGOOD[n]
OK ?
Disable All Regulators,
Display Error Message
Execute Slot delay
for rail n
n <= Number of
Channels
End Sequencing
n = n + 1
Y
N
Y
N
Is restart switch
pressed ?
Y
N