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CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. **
Example Project
Figure 3-10. Margin and Trim Circuit for the V3=2.5-V Rail
Margining is similar to trimming but is used for manufacturing test purposes. In this case, the rails
are intentionally set to their upper or lower limits to enable system designers to verify that their sys-
tems work at both extremes of the voltage rail tolerances. For example, if a 5-V rail is used in the
system and specified to have an accuracy of ± 5%, margining will set the rail to 5 V –5% to enable
system verification. Then the rail can be margined to the high side of 5 V +5% and the system veri-
fied again. This capability exists on all four rails controlled by PSoC 1 in this example project.
The trimming feature works based on the ‘Trim Percentage’ parameter. This configurable parameter
indicates the amount to which the rail voltage must be trimmed in terms of percentage of nominal
voltage of that rail. Each of the rails can have a different trim percentage. By default, the trim per-
centages is set to ‘0’ to get the expected rail voltages. However, there will be trimming error of at
least 4 mV because of ADC measurement resolution of 4 mV. To change the trim percentages, the
definitions must be changed in the
configuration.h
file of the project, as shown here.
3.4.5
Other Features
■
I2C/SMBus/PMBus interface to a host CPU (available on the white 5-pin header on the EBK).
■
EEPROM for calibration/configuration parameters, fault logging, and so on.
Detailed description of how to make use of those features is not currently covered by this document.
Example projects covering these topics in more detail will be added in the future.
3.4.6
Firmware Flowchart
The firmware has the following initialization steps:
1. Display the introductory message and initialize the system parameters
2. Check for EBK connectivity and wait until it is connected
3. Initialize PWM trim/margin hardware
4. Initialize fault detection hardware
Summary of Contents for CY8CKIT-015
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