Cypress Semiconductor CY8CKIT-015, Manual

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CY8CKIT-015 PSoC 1 Power Supervision Kit Guide, Doc. # 001-81218 Rev. ** 17
Example Project
SEQUENCING_MODE_1 to SEQUENCING_MODE_6. This changes the sequencing order of the
rails.
Similarly, you can change the ramp delays and slot delays to be used for sequencing by changing
the default delays in the same header file. The entered delay must be in msec. from 1 to 1300.
3.4.2 UV and OV Monitoring using Window Comparator
To support under-voltage (UV) and over-voltage (OV) fault detection on the four secondary power
supply rails, eight comparators and eight programmable DACs are required. As the number of regu-
lators in the systems expands, the number of comparators and DACs required becomes excessive.
To make more efficient use of analog hardware resources, an alternative implementation is provided.
As shown in Figure 3-9 , a single window comparator and glitch filter are time-multiplexed across all
the rails requiring monitoring. The voltage regulator output for rail[n] (signal V[n]) of the power rail is
compared against the OV and UV thresholds using two hardware comparators. If the voltage level is
not within these thresholds, the appropriate comparator generates the fault signal.
Figure 3-9. Time Multiplexed OV and UV Fault Detection Hardware
The UV comparator checks for under-voltage fault; output will be high if there is a fault. The OV com-
parator checks for over-voltage fault; output (after the inverter) will be high if there is a fault. Eight-bit
DACs are used to generate the user-defined UV and OV thresholds.
MUX
PGOOD Signal
routed to a GPIO
UV Glitch
Filter
OV Glitch
Filter
+
_
+
_
UV Comparator
OV Comparator
Inverter
NOR Gate
OV Fault indicator
routed to another GPIO
UV Threshold
DAC
OV Threshold
DAC
Scaled down rail
voltages