Curtiss-Wright FHK4-FM4MWB04-00 Hardware Reference Manual Download Page 49

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6. APPENDIX B - REGISTER SET

TABLE OF CONTENTS

6.1 Overview .................................................................................................................................. 6-1

6.1.1 Interrupt CSR (INT_CSR) – Offset 0x00 .............................................................. 6-1

6.1.2 Board CSR (BRD_CSR) – Offset 0x04 ................................................................. 6-2

6.1.3 Link Control (LINK_CTL) – Offset 0x08 ............................................................. 6-3

6.1.4 Link Status (LINK_STAT) – Offset 0x0C ............................................................ 6-6

6.1.5 FPDP Flags (FPDP_FLGS) – Offset 0x10 ............................................................ 6-7

6.1.6 Receive FIFO Threshold– Offset 0x14 .................................................................. 6-8

6.1.7 Laser Transmitter Control – Offset 0x18 ............................................................... 6-8

Summary of Contents for FHK4-FM4MWB04-00

Page 1: ... SL100 SL240 Hardware Reference for Carrier and Rehostable CMC FPDP Legacy Cards F T MR S3FPDP A 0 B1 ...

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Page 3: ...s for a particular purpose Copyright 2012 Curtiss Wright Controls Inc All Rights Reserved SL100 SL240 Dual Port Memory FIFO U S Patent 6 259 648 is a registered trademark of Curtiss Wright Controls Inc is a registered trademark of Curtiss Wright Controls Inc is a registered trademark of Curtiss Wright Controls Inc Any reference made within this document to equipment from other vendors does not con...

Page 4: ...n which may interfere with other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE As a component part of another system this product has no intrinsic function and is therefore not subject to the European Union CE EMC directive 89 336 EEC ...

Page 5: ... 7 2 5 4 Single Master Ring 2 8 2 5 5 Multiple Master Ring 2 9 2 6 Status LEDs 2 10 2 6 1 SL240 CMC LEDs 2 10 2 6 2 PCI Carrier Card Status LEDs 2 11 3 INSTALLATION 3 1 3 1 Installation Procedures 3 1 3 2 Unpack the Card 3 1 3 3 Inspect the Card 3 1 3 4 Install the Card 3 2 3 4 1 PCI FibreXtreme Carrier Card Installation 3 2 3 4 2 Rehostable CMC Card Installation 3 2 3 5 Configure the Cards 3 3 3 ...

Page 6: ...etup 7 2 7 3 PCI FibreXtreme Carrier Card Register Offsets 7 3 7 3 1 PIO and Carrier Configuration Offset 0x0 7 3 7 3 2 Reserved Register Offset 0x1 7 3 7 3 3 CMC Configuration Offset 0x2 7 4 7 3 4 Reserved Register Offset 0x3 7 4 7 4 CMC Register Offsets 7 5 7 5 PCI FibreXtreme Carrier Configuration Commands 7 5 7 5 1 Active Configuration ac 7 5 7 5 2 Edit Configuration ec configuration 7 5 7 5 3...

Page 7: ... Interconnects 11 8 11 4 3 Destination Card Signal Interconnects 11 12 11 5 Programmed Inputs Outputs PIOs 11 16 11 6 Thermal Specifications 11 17 11 7 Electrical Specifications 11 17 11 7 1 DC Characteristics 11 17 11 7 2 AC Characteristics 11 18 11 8 Transmitting Data 11 19 11 9 Microcontroller Interface 11 20 APPENDICES APPENDIX A SPECIFICATIONS 5 1 APPENDIX B REGISTER SET 6 1 APPENDIX C CARRIE...

Page 8: ...nts for SL240 3 5 Table 5 1 FPDP Connector Pin Assignments 5 3 Table 5 2 PCI FibreXtreme Carrier Card s RS 232 Pin Assignments 5 4 Table 8 1 Ordered Set Mapping 8 2 Table 8 2 Maximum Sustained Throughput 8 4 Table 8 3 Sampling Frequencies 8 4 Table 9 1 SL100 CMC Standard 9 1 Table 9 2 SL240X CMC Standard 9 1 Table 9 3 Carrier Card Without CMC 9 1 Table 9 4 Multimode Fiber Optic Cable LC LC 9 2 Tab...

Page 9: ...breXtreme SL240 family of products Applications and topologies for SL240 cards Instructions for installing and configuring the cards An operational overview of the product General card specifications Register set information Configuration information Summary of the protocol used by the SL240 cards Ordering information for all products mentioned in this manual A brief introduction to the Front Pane...

Page 10: ...86 Draft 2 0 April 4 1995 Fibre Channel Association Product Information Bulletin Revision December 9 1994 Fibre Channel Physical and Signaling Interface FC PH Revision 4 3 June 1 1994 Produced by the ANSI X3T9 3 standards group Fibre Channel Physical and Signaling Interface 2 FC PH 2 Revision 7 3 January 5 1996 Produced by the ANSI X3T11 standards group Fibre Channel Physical and Signaling Interfa...

Page 11: ...tion procedures Improve the quality of our operations to meet the needs of our customers suppliers and other stakeholders Provide our employees with the tools and overall work environment to fulfill maintain and improve product and service quality Ensure our customer and other stakeholders that only the highest quality product or service will be delivered The British Standards Institution BSI the ...

Page 12: ...make this document comprehensive you may have specific problems or issues this document does not satisfactorily cover Our goal is to offer a combination of products and services that provide complete easy to use solutions for your application If you have any technical or non technical questions or comments contact us Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time P...

Page 13: ...cy The protocol involved for this transport is based on Fibre Channel though it is not Fibre Channel compliant The major SL240 features are listed below Uses proven 8B 10B encoding for data transmission End to end throughput of 247 MBps with or without frame checksums SL240 End to end throughput of 105 MBps with or without frame checksums SL100 Minimizes implementation cost and enhances throughput...

Page 14: ...hort wavelength version is useful for intrasystem connections such as connecting between cards on the same backplane It is also suited for short reach intersystem connections 300 m HSSDC interconnections are recommended for very short distances of 30 meters or less All cards use a Duplex LC style connector or HSSDC2 receptacle available from most major cable manufacturers For details concerning th...

Page 15: ...lications where it is desired to change the FPDP port data direction via software control and a PCI form factor is required Features PCI form factor One FPDP port configurable for input or output Αccepts one SL100 SL240 CMC card Configurable using a microcontroller interface via an RS 232 port Offers access to SL100 SL240 CMC card s register set Supports the following FPDP transmitter bus speeds T...

Page 16: ...Small Form Factor Pluggable XFP modules FW1600 48 port IEEE 1394b Firewire copper media ET1000 48 port auto negotiation 10 100 or 1000 Mbps Ethernet with RJ 45 connectors Contact Curtiss Wright Controls for a complete list of available port cards Port cards and pluggable transceivers may be mixed in one system Supports Loop Point to Point One to Many communication links Supports multiple physical ...

Page 17: ...t rate However the figure is also applicable to SL240 by changing the data throughput rate to 247 MBps CMC CMC Sensors Scan the Image DSP Systems Develop the Image High Performance General Purpose Computers Analyze the Image High Speed Storage Radar IR Sonar Acoustic Photon Video Etc 105 MBps 100 MBps 105 MBps 105 MBps SL100 SL240 Fibre Channel FULL FC 4 FIBRE CHANNEL IS GOOD FOR STORAGE WORKSTATI...

Page 18: ...tending FPDP 2 5 Topologies 2 5 1 Typical Topologies There are four typical topologies for the SL240 card These topologies should cover most customer applications though if another topology is desired contact Curtiss Wright Controls Technical Support to see if it is possible The topologies are Point to point Chained Single Master Loop Multiple Master Loop 2 5 2 Point to point The point to point to...

Page 19: ...40X Card SL240X Card Figure 2 5 Point to Point Topology 2 5 3 Chained This topology is a single transmitter on the end of a long string of receivers No flow control is available in this topology and the distance between the nodes is limited only by the transceivers used 10 km typical 26 km maximum This topology is good for broadcasting data to multiple destinations where late data is of no use suc...

Page 20: ...itch suitable for this purpose is the LinkXchange GLX4000 available from Curtiss Wright Controls Inc Software controls mastership switching of the ring There are rules associated with master switching listed in the Programming Interface section The flow control used in this case is similar to a multi drop FPDP bus where any receiver can back the transmitter off This is the typical configuration fo...

Page 21: ...m the previous master and sends data to the next master No flow control is allowed in this topology for rings above two nodes and the data cannot be passed through masters unless control guarantees that there is at least one source only node on the ring and that no two masters will transmit at the same time Single master rings should temporarily become multiple master rings when switching loop mas...

Page 22: ... This LED is reserved for future use The on off condition of this LED is of no consequence Link Up LU The Link Up LED turns on when receiving a valid SL240 signal Signal Detect RX The Signal Detect LEDs indicate a signal is being received by the transceiver This LED gives no indication of the validity of the signal only that a signal is present Laser Enable TX The Laser Enable LEDs indicate the tr...

Page 23: ...led RX OK is lit it indicates no errors have occurred on the FPDP receive interface or the link transmit interface When this LED is not lit the link interface is down and flow control is not ignored Transmit Interface TX OK When the LED labeled TX OK is lit it indicates no errors have occurred on the FPDP transmit interface or the link receive interface When this LED is not lit any one of the foll...

Page 25: ... may cause permanent damage to the components on the card Follow the steps below to unpack the card 1 Put on a wristband attached to an anti static mat 2 Remove the card and anti static bag from the carton 3 Place the bag on the anti static mat 4 Open the anti static bag and remove the card 5 In the unlikely event you need to return your SL240 card please keep the original shipping materials for t...

Page 26: ...her card as shown in Figure 3 1 steps 1 and 2 until it is firmly seated Install the mounting screw as shown in step 3 NOTE The PCI FibreXtreme Carrier card only uses 5 volt power and ground from the PCI bus As a result it can be plugged into any PCI PCI X slot 3 3 or 5 volt without impact on PCI PCI X bus throughput Figure 3 1 SL240 PCI Card Installation 3 4 2 Rehostable CMC Card Installation Sinc...

Page 27: ...gent s part number for the ribbon cable connector is P50E 080S TG Robinson Nugent P50E 080P1 SR1 TG connectors or equivalents may be used for VME and PCI FPDP carrier cards 80 pin ribbon cable PCB Robinson Nugent RN PAK 50 Connectors connector connector P50E 080S TG P50E 080P1 SR1 TG Figure 3 2 FPDP Connectors NOTE Curtiss Wright Controls Inc does not provide the FPDP cables Please use the Robinso...

Page 28: ... dirt and dust can interfere with the light signal transmission Use an alcohol based wipe to clean the cable ends For short wavelength laser modules either a 50 µm or 62 5 µm core diameter cable should be used A 62 5 µm cable can be used for distances up to 300 m 50 µm cable allows distances up to 500 m For distances greater than 500 m up to 10 km long wavelength laser modules with 9 µm core cable...

Page 29: ...in Description 1 Ground 5 Transmit 2 Receive 6 Transmit 3 Receive 7 Ground 4 Ground Table 3 2 HSSDC2 Receptacle Pin Assignments for SL240 Pin Number Pin Description 1 Ground 2 Receive 3 Receive 4 Ground 5 Transmit 6 Transmit 7 Ground To insure data integrity take care when selecting the appropriate HSSDC2 cable assembly for the SL100X SL240 application Application data rate and the presence of equ...

Page 30: ...istance Please be prepared to supply the following information Machine __________________________________________ OS Name __________________________________________ OS Version __________________________________________ Card Type __________________________________________ Card Serial __________________________________________ Software Part __________________________________________ Software S N ___...

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Page 33: ...is kept minimal to reduce the latency and improve throughput while still providing a set of useful features for users to customize their applications The hardware is designed to offer many different features for advanced applications while maintaining a simple interface to the most commonly used features NOTE For further explanation of terms used in the following sections consult the FPDP Primer l...

Page 34: ...ration In the Loop Operation discussion below SL100 SL240 is used generically to refer to any Curtiss Wright Controls SL100 SL240 card Anything that applies to only a specific SL100 SL240 product will be noted as such Loop operation with the SL100 SL240 acts like a virtual FPDP bus where one source the loop master can transmit to any number of receive nodes The link protocol is the same for this o...

Page 35: ...ster set if applicable If placed in the register set they can be accessed by a microcontroller via the optional microcontroller interface on the CMC carrier The use of DIR and NRDY is consistent with the use of flow control retransmission of a STOP request for loop operation See the ANSI VITA 17 1 Serial FPDP specification for additional details Note that NRDY as a Serial FPDP signal has no direct...

Page 36: ...ected normally 4 4 2 Loop Enable The loop enable option allows the SL240 card to transmit the Serial FPDP received data stream again Turning on the loop enable implies that this node is designated as a receiver in the current configuration 4 4 3 Receiver Transmitter Enable The transmitter and receiver enable bits in the Link Control register turn off the transmit and receive Serial FPDP data strea...

Page 37: ... you to stop data from being received from the Receive FIFO when a SYNC without DVALID is received on the output 4 4 6 Receive FIFO Threshold Interrupt SL240 cards can be configured to interrupt the host when the FIFO passes a certain threshold allowing for efficient PIO transactions out of the Receive FIFO This is particularly important on data storage systems where you do not want to remove data...

Page 39: ...fications 5 2 5 4 FPDP Connector Pin Assignments 5 3 5 5 RS 232 Pin out on PCI FibreXtreme Carrier 5 4 5 6 Media Interface Specifications 5 5 5 6 1 SL100 Fiber Optic Media Interface Specifications 5 5 5 6 2 SL240 Fiber Optic Media Interface Specifications 5 5 5 6 3 SL100 HSSDC2 Copper Media Interface 5 6 5 6 4 SL240 HSSDC2 Copper Media Interface 5 6 ...

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Page 41: ...tions Hardware Compatibility CMC IEEE P1386 Physical Dimensions 2 91 x 5 87 inches 74 x 149 mm Weight 0 25 lb Power Dissipation SL100 5 1 W Peak 3 1 W Average SL240 7 4 W Peak 4 3 W Average Electrical Requirements SL100 5 VDC 1 02 Amps Peak 0 62 Amps Average SL240 5 VDC 1 48 Amps Peak 0 86 Amps Average Operating Temperature Range 0 to 50 C Mean Time Between Failure MTBF SL100 Short wavelength lase...

Page 42: ...al Requirements SL100 5 VDC 0 3 Amps SL240 5 VDC 0 3 Amps Operating Temperature Range 0 to 50 C Mean Time Between Failure MTBF PCI FibreXtreme Carrier without CMC card 395 042 hours 45 1 years Storage Temperature Range 40 to 85 C Maximum FPDP Node Separation 1 to 5 m application dependent The MTBF numbers are based on calculations using MIL HDBK 217F Appendix A and Bellcore 332 Issue 6 for a groun...

Page 43: ...ignments Pin Row A Row B Row C Row D 1 GND 1 STROBE 2 GND 3 GND 4 2 GND 5 GND 6 NRDY 7 GND 8 3 DIR 9 GND 10 RESERVED 11 GND 12 4 SUSPEND 13 GND 14 GND 15 GND 16 5 PIO2 17 GND 18 PIO1 19 GND 20 6 RESERVED 21 GND 22 RESERVED 23 GND 24 7 PSTROBE 25 GND 26 PSTROBE 27 GND 28 8 SYNC 29 GND 30 DVALID 31 GND 32 9 D31 33 D30 34 GND 35 D29 36 10 D28 37 GND 38 D27 39 D26 40 11 GND 41 D25 42 D24 43 GND 44 12 ...

Page 44: ...Not Connected 2 RTS Not Connected 3 GND 4 TxD Out 5 RxD In 6 GND 7 CTS Not Connected 8 DTR Not Connected A 14 foot RJ 45 straight cable and RJ 45 Female to DB 9 Female Adapter are provided with each PCI FibreXtreme Carrier card These items can be used to connect the PCI FibreXtreme Carrier card s RJ 45 connector to a personal computer s DB 9 serial port DB 9 Female DCD 1 DSR 6 RTS 7 GND 5 TxD 3 Rx...

Page 45: ... mode fiber low cost long distance Maximum Fiber Length 10 km Transmit Wavelength 1285 to 1330 nm Transmit Power 9 to 3 dBm Receive Wavelength 1100 to 1600 nm Receive Sensitivity 20 to 3 dBm 1550 nm Media 8 3 125 µm single mode fiber Maximum Fiber Length 51 km Transmit Wavelength 1535 to 1565 nm Transmit Power 2 to 5 dBm Receive Wavelength 1535 to 1565 nm Receive Sensitivity 26 to 3 dBm 5 6 2 SL24...

Page 46: ... Receive Sensitivity 30 to 6 dBm 5 6 3 SL100 HSSDC2 Copper Media Interface Cable 150 Ohm shielded Quad Maximum Cable Length Up to 30 meters with equalized cable Compatibility 1 Gbps shielded balanced cable Connector HSSDC2 Fibre Channel Style 2 Data Rate 1 0625 Gbps 5 6 4 SL240 HSSDC2 Copper Media Interface Cable 100 Ohm shielded Quad Maximum Cable Length Up to 10 meters with equalized cable Compa...

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Page 49: ...T_CSR Offset 0x00 6 1 6 1 2 Board CSR BRD_CSR Offset 0x04 6 2 6 1 3 Link Control LINK_CTL Offset 0x08 6 3 6 1 4 Link Status LINK_STAT Offset 0x0C 6 6 6 1 5 FPDP Flags FPDP_FLGS Offset 0x10 6 7 6 1 6 Receive FIFO Threshold Offset 0x14 6 8 6 1 7 Laser Transmitter Control Offset 0x18 6 8 ...

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Page 51: ...are this resets the microcontroller on the PCI FibreXtreme Carrier card and causes the active register configuration to be reloaded from the EEPROM This may be fixed in a future firmware revision and these bits will work as described in this manual Bit Description Access Reset Value 3 to 0 Reserved None 0 4 Link Error Interrupt A 1 indicates active a 0 indicates not active Write 1 to clear R WOC 0...

Page 52: ... R W 0 6 JTAG TDI TDI line from the JTAG port R 1 7 JTAG Enable Enable the JTAG port on the FPGA R W 0 14 to 8 Revision ID Revision level of the card controller R See desc 15 SL100 SL240 A 1 indicates this is an SL240 card a 0 indicates this is an SL100 card R See desc 23 to 16 Extended Revision ID These bits are used to identify intermediate or special firmware revisions Bit 23 0 indicates the Co...

Page 53: ...errors R W 0 2 Ignore Flow Control Set to 1 to ignore flow control from the remote end and continue transmitting when the link is down Set to 0 to stop transmission when the link goes down or the remote end is sending a STOP ordered set back NOTE In almost every application flow control should be enabled Even if the application must sustain maximum link throughput it is better to drop the data at ...

Page 54: ...am A 1 indicates the outgoing data stream is electronically wrapped into the incoming data stream at the serializer deserializer A 0 indicates non wrapped data flow to and from the link interface This is typically used for testing purposes R W 0 11 LWRAP This signal controls the loopback operation of the link interface s data stream and implements the Copy Mode described in the ANSI VITA 17 1 Seri...

Page 55: ...L240 FPGA logic can cause undesirable effects because each 32 bit Serial FPDP data word occupies two entries in the respective FIFO and the link and host are independently filling and draining these FIFOs Applying the FIFO resets without applying special precaution can result in a misalignment of data in these FIFOs W 0 20 Erase RX FIFO Set to a 1 to reset the Receive FIFO This bit is included for...

Page 56: ...ed like the Link Down bit R 0 10 Synchronization Error A 1 indicates the card has corrected a synchronization error on the incoming data stream A 0 indicates the card has not corrected a synchronization error on the incoming data stream This bit is cleared through Reset SR in LINK_CTL R 0 11 Checksum Error A 1 indicates the card has detected a checksum error on the incoming data stream A 0 indicat...

Page 57: ...that a STOP flow control primitive was sent to the remote transmitter This bit is read only and will be dynamically changing R 0 15 FIFO Overflow Indicates that the Remote Transmitter FIFO Overflow bit was set in the received Status End of Frame primitive EOFa or EOFn Fibre Channel ordered sets This indicates that the remote node detected an overflow condition in its transmit FIFO This bit is read...

Page 58: ... Receive FIFO R 0 20 Rearm Threshold Interrupt Write 1 to rearm the threshold register Writing 0 has no effect W 0 21 Data present A 1 indicates data is present on the output A 0 indicates no data is present R 0 29 to 22 Reserved None 0 31 to 30 Interrupt Threshold Selects one of the following levels of the Receive FIFO to interrupt on 00 Interrupt threshold set to Receive FIFO Not Empty 01 Interr...

Page 59: ...rrier Configuration Commands 7 5 7 5 1 Active Configuration ac 7 5 7 5 2 Edit Configuration ec configuration 7 5 7 5 3 Get Configuration gc configuration 7 6 7 5 4 Load Configuration lc configuration 7 6 7 5 5 Set Configuration sc configuration 7 6 7 5 6 Bus Read br register set address 7 7 7 5 7 Bus Write bw register set address 7 7 7 5 8 Help h 7 7 7 6 PCI Carrier Card Default Configurations 7 8...

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Page 61: ...lications It offers excellent coverage of data errors and has very little impact on link throughput for maximum frame sizes The option of disabling CRC is only retained for compatibility with older third part devices Both nodes on the link or all nodes in a loop configuration should be set to a common CRC mode or the resulting mismatch will cause data errors and or link errors NOTE In almost every...

Page 62: ... emulation program configure the COM port with these settings 9600 Baud 8 data bits 1 stop bit no parity The fiber optic loopback cable connected to the rehostable CMC card s laser transceiver is optional However it is nice because it allows the Link Up LED on the CMC card to turn on after the CMC card s configuration process This is the only visible indicator that the CMC card is configured RS 23...

Page 63: ...M or an FPDP RM Set to 0 if this card is an FPDP R 0 3 Transmit Set to 1 if this card is an FPDP TM Set to 0 if this card is an FPDP RM or an FPDP R 0 4 PIO1 Reversed If 0 PIO1 maps to PIO1_IN or PIO1_OUT depending on PIO1 Direction If 1 PIO1 maps to PIO2_IN or PIO2_OUT depending on PIO1 Direction 0 5 PIO2 Reversed If 0 PIO2 maps to PIO2_IN or PIO2_OUT depending on PIO2 Direction If 1 PIO2 maps to...

Page 64: ... is used For all FPDP operations set to 0 When set to 1 a SYNC without DVALID is appended after every SYNC with DVALID from the link 0 4 to 3 FPDP TM Clock Configuration Controls the FPDP transmitter clock frequency The FPDP transmitter clock is the reference clock 53 125 MHz or 125 MHz divided by 2 4 3 or 6 The clock divisions available for standard cards are 0 CLK_CFG0 Bit 4 CLK_CFG1 Bit 3 SL100...

Page 65: ...lt configurations NOTE All numbers entered or displayed using this configuration software are hexadecimal 7 5 1 Active Configuration ac This command displays the number of the current active configuration The active configuration is the configuration loaded from the EEPROM every time the carrier card is powered on 7 5 2 Edit Configuration ec configuration This command allows a configuration stored...

Page 66: ...ately loads a stored configuration from the EEPROM However this command does not change the active configuration loaded at power up The sc command must be used to change the active configuration The lc command has the following parameter configuration One of four possible register configurations identified as 0 1 2 or 3 WARNING It is sometimes necessary to power cycle the carrier card for the new ...

Page 67: ...rs Any registers written using the bw command are lost when power is removed from the carrier CMC cards This command is typically used only for debugging The current value of a register is shown before the colon A new register value may be entered after the colon followed by pressing the E key If the current register value is already correct press the E key by itself This will keep the existing va...

Page 68: ... with CRC Disabled VME 0 0C 1 00 2 40 3 00 CMC 00 00000000 04 00000000 08 00000001 0C 00000000 10 00000000 14 00000000 18 00000000 1C 00000000 7 6 2 Configuration 1 FPDP RM with CRC Disabled VME 0 04 1 00 2 40 3 00 CMC 00 00000000 04 00000000 08 00000000 0C 00000000 10 00000000 14 00000000 18 00000000 1C 00000000 7 6 3 Configuration 2 FPDP TM with CRC Enabled VME 0 0C 1 00 2 40 3 00 CMC 00 0000000...

Page 69: ...opyright 2012 7 9 FibreXtreme HW Reference for FPDP Cards 7 6 4 Configuration 3 FPDP RM with CRC Enabled VME 0 04 1 00 2 40 3 00 CMC 00 00000000 04 00000000 08 00000002 0C 00000000 10 00000000 14 00000000 18 00000000 1C 00000000 ...

Page 71: ... 8 1 8 2 Ordered Sets Used 8 1 8 3 Frames 8 3 8 3 1 Link Bandwidth 8 4 8 3 2 FPDP Signal Sample Rate 8 4 8 4 Data Transmission and Flow Control 8 5 TABLES Table 8 1 Ordered Set Mapping 8 2 Table 8 2 Maximum Sustained Throughput 8 4 Table 8 3 Sampling Frequencies 8 4 ...

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Page 73: ... the transmission words in the 8B 10B protocol to be ordered sets which denote special control information for Fibre Channel These same ordered sets are used in ANSI VITA 17 1 but are assigned different meaning There are eighteen ordered sets used by SL240 to denote different information Twelve of these ordered sets are used to embed five bits of data eight start of frame SOF sets are used to embe...

Page 74: ...Fn3 SOF Start of Frame PIO1 1 PIO2 1 DIR 0 SOFf SOF Start of Frame PIO1 1 PIO2 1 DIR 1 EOFt SEOF Status EOF FIFO Overflow 0 NRDY 0 EOFdt SEOF Status EOF FIFO Overflow 0 NRDY 1 EOFa SEOF Status EOF FIFO Overflow 1 NRDY 0 EOFn SEOF Status EOF FIFO Overflow 1 NRDY 1 EOFni MEOF Mark EOF EOF for a SYNC frame EOFdti FEOF Frame EOF EOF for a normal data frame R_RDY SWDV SYNC with DATA Valid Says that the...

Page 75: ...n the output of the Transmit FIFO the current frame is terminated and the proper SYNC frame SYNC with data or SYNC without data is sent Figure 8 1 shows the four types of frames and the ordered set placement within those frames IDLE SOF CRC GO STOP SEOF FEOF IDLE Fiber Frame IDLE SOF CRC GO STOP SEOF FEOF 1 To 512 4 Byte Data Words Maximum 2048 Bytes Data Fiber Frame SWDV SOF CRC GO STOP SEOF MEOF...

Page 76: ...opy Mode Master bit 1 SL100 105 02 MBps 105 22 MBps 104 41 MBps 104 61 MBps SL240 247 10 MBps 247 58 MBps 245 68 MBps 246 15 MBps NOTE The Copy Master Mode is located in the Link Control register 8 3 2 FPDP Signal Sample Rate The states of the FPDP signals PIO1 PIO2 DIR and NRDY are transmitted across the link at varying rates The worst case rate at which these signals are sampled is for CRC check...

Page 77: ...al changes Curtiss Wright Controls SL100 SL240 cards use the same protocol when transmitting from either end to allow the link to operate bi directionally Since these data streams are independent the maximum throughput on the link would be 210 MBps 105 MBps direction for SL100 or 494 MBps for SL240 The receiver should transmit the STOP signal when it has space for the data contained in 20 km of fi...

Page 79: ... HSSDC2 Copper Media Interface 2 5 Gbps 9 4 TABLES Table 9 1 SL100 CMC Standard 9 1 Table 9 2 SL240X CMC Standard 9 1 Table 9 3 Carrier Card Without CMC 9 1 Table 9 4 Multimode Fiber Optic Cable LC LC 9 2 Table 9 5 Multimode Fiber Optic Cable LC ST 9 2 Table 9 6 Multimode Fiber Optic Cable SC LC 9 2 Table 9 7 Singlemode Fiber Optic Cable LC LC 9 3 Table 9 8 Singlemode Fiber Optic Cable SC LC 9 3 T...

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Page 81: ...tion 2 3 for detailed descriptions of the various SL100 FPDP ordering configurations Table 9 1 SL100 CMC Standard Order Number Description FHK4 FM4MWB04 00 SL100 CMC SFP 850 nm laser 9 2 2 SL240X FPDP Refer to section 2 3 for detailed descriptions of the various SL240X FPDP ordering configurations Table 9 2 SL240X CMC Standard Order Number Description FHK6 FM6MWB04 00 SL240X CMC SFP 850 nm laser 9...

Page 82: ...HAC M1LCxxxx 00 FHAC M2LCxxxx 00 Custom LC LC Table 9 5 Multimode Fiber Optic Cable LC ST Simplex Part Number Duplex Part Number Length Cable End 1 Cable End 2 FHAC M1LCST03 00 FHAC M2LCST03 00 3 m LC ST FHAC M1LCST05 00 FHAC M2LCST05 00 5 m LC ST FHAC M1LCST10 00 FHAC M2LCST10 00 10 m LC ST FHAC M1LCST20 00 FHAC M2LCST20 00 20 m LC ST FHAC M1LCST30 00 FHAC M2LCST30 00 30 m LC ST FHAC M1LCSTxx 00 ...

Page 83: ...x Part Number Length Cable End 1 Cable End 2 FHAC S1SCLC01 00 FHAC S2SCLC01 00 1 m SC LC FHAC S1SCLC03 00 FHAC S2SCLC03 00 3 m SC LC FHAC S1SCLC05 00 FHAC S2SCLC05 00 5 m SC LC FHAC S1SCLC10 00 FHAC S2SCLC10 00 10 m SC LC FHAC S1SCLC20 00 FHAC S2SCLC20 00 20 m SC LC FHAC S1SCLC30 00 FHAC S2SCLC30 00 30 m SC LC FHAC S1SCLCxx 00 FHAC S2SCLCxx 00 Custom SC LC 9 3 3 HSSDC2 Copper Media Interface 1 062...

Page 84: ...ble with HSSDC2 InfiniBand connectors for use with the HSSDC2 copper media interface Table 9 10 Shielded 100 Ohm Quad Copper Cable with HSSDC2 InfiniBand Connectors Order Number Description FHAC Q2H31000 00 1 m HSSDC2 cable equalized FHAC Q2H33000 00 3 m HSSDC2 cable equalized FHAC Q2H35000 00 5 m HSSDC2 cable equalized FHAC Q2H31001 00 10 m HSSDC2 cable equalized ...

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Page 87: ...Theory of Operation 10 3 10 3 1 Clock Signals 10 3 10 3 2 Data Framing 10 3 10 4 Serial FPDP Theory of Operation 10 5 10 5 Parallel FPDP Signal Timing 10 5 FIGURES Figure 10 1 Example Configuration With Multiple VME FPDP SL240 Carrier Cards 10 2 Figure 10 2 Parallel FPDP Interface Timing Diagram 10 7 TABLES Table 10 1 Parallel FPDP Timing Specifications 10 9 Table 10 2 FPDP Transmitter Interface T...

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Page 89: ...not provide the required bandwidth and latency at all times because of bus contention The primary bus must also handle other tasks such as system control The FPDP bus provides a solution to this problem Using FPDP two or more cards are connected by a simple parallel synchronous interface using 80 conductor ribbon cable running across the cards front panels or through a 1 0625 Gbps or 2 5 Gbps seri...

Page 90: ...r PCI traffic can continue without data transfers wasting bus bandwidth No bus contention is possible because there is only one transmitter No special backplane is required FPDP allows connections from VME chassis to VME chassis Systems may have multiple FPDP buses and thus provides scaleable bandwidth Multiple FPDP busses may coexist in one chassis Throughput can be accurately computed in the des...

Page 91: ...he timing signals provided by the FPDP TM As opposed to the FPDP RM this device does not terminate any bus signals on parallel FPDP Multiple FPDP R devices may exist on an FPDP bus 10 3 Parallel FPDP Theory of Operation 10 3 1 Clock Signals A single FPDP TM generates a free running clock This clock frequency determines the maximum transfer rate on the bus FPDP provides both a PECL Positive Emitter...

Page 92: ...DP bus the FPDP TM must assert a SYNC pulse before valid data starts being transmitted Valid data is transmitted when the data valid signal DVALID is asserted Thus a SYNC pulse must be asserted before DVALID is asserted when transmitting single frame data After a SYNC pulse is asserted the FPDP RM and FPDP R devices should not accept data until the first STROBE period after DVALID is asserted The ...

Page 93: ...he parallel FPDP version due to link framing overhead and the fact that the link operates asynchronously to the parallel FPDP frequencies 10 5 Parallel FPDP Signal Timing Figure 10 2 shows the timing for several FPDP interface signals This figure is accurate for all four data framing types See section 10 3 2 for a discussion of framing The Data Valid signal DVALID is asserted by the FPDP TM when v...

Page 94: ...signal from the link interface to the FPDP interface An SL240 FPDP R or FPDP RM inverts and passes this signal from the FPDP interface to the link interface DIR is an active high signal on the link interface DIR is an active low signal on the FPDP interface Two user defined Programmable I O PIO signals PIO1 and PIO2 are reserved in the Front Panel Data Port Specifications These are auxiliary signa...

Page 95: ... VALID VALID VALID VALID VALID VALID VALID VALID XXXX XXXX XXXX DVALID D 31 0 SYNC XXXX VALID SUSPEND D 31 0 DVALID STROBE VALID VALID VALID VALID VALID XXXX VALID VALID XXXX XXXX VALID VALID VALID NRDY PSTROBE PSTROBE STROBE 1 2 4 3 Figure 10 2 Parallel FPDP Interface Timing Diagram ...

Page 96: ...LID XXXX XXXX STROBE DVALID D 31 0 SYNC XXXX VALID SYNC D 31 0 DVALID STROBE VALID VALID VALID VALID VALID VALID VALID XXXX XXXX XXXX XXXX XXXX XXXX VALID VALID VALID VALID A SINGLE FRAME DATA B FIXED SIZE AND DYNAMIC SIZE REPEATING FRAME DATA 1 2 2 1 Figure 10 3 FPDP Timing Diagrams Showing the Use of Framing ...

Page 97: ...s Parameter Description At Transmitter End of Cable At Receiver End of Cable FPDP Clock Used 1 Data DVALID SYNC setup time 6 0 ns min 5 0 ns min TTL 1 Data DVALID SYNC setup time 5 5 ns min 4 5 ns min PECL 2 Data DVALID SYNC hold time 12 8 ns min 11 8 ns min TTL 2 Data DVALID SYNC hold time 12 0 ns min 11 0 ns min PECL Table 10 2 FPDP Transmitter Interface Timing Specifications Parameter Descripti...

Page 99: ...figuration Signal Interconnects 11 3 11 4 2 Source Card Signal Interconnects 11 8 11 4 3 Destination Card Signal Interconnects 11 12 11 5 Programmed Inputs Outputs PIOs 11 16 11 6 Thermal Specifications 11 17 11 7 Electrical Specifications 11 17 11 7 1 DC Characteristics 11 17 11 7 2 AC Characteristics 11 18 11 8 Transmitting Data 11 19 11 9 Microcontroller Interface 11 20 ...

Page 100: ...d 11 20 Figure 11 9 Microcontroller Single Write 11 21 TABLES Table 11 1 Connectors to Interface the SL240 Rehostable CMC Card 11 2 Table 11 2 FPDP Configuration Interface P3 11 4 Table 11 3 Signal Descriptions for FPDP Configuration Interface P3 11 5 Table 11 4 FPDP Receiver Interface P6 11 10 Table 11 5 Signal Descriptions for FPDP Receiver Interface P6 11 11 Table 11 6 FPDP Transmitter Interfac...

Page 101: ...or the CMC card 11 2 Mechanical Details The SL240 rehostable CMC FPDP card is a single CMC as defined in IEEE P1386 There is one deviation from this standard on the card it includes a P6 connector not listed in the specification This card complies with the height requirements defined in IEEE P1386 Figure 11 1 shows the connector placement as well as other dimensions D2 RX D1 TX D4 LS D3 LU D2 D4 3...

Page 102: ...e throughout this manual the term FPDP receiver is synonymous with source card and FPDP transmitter is synonymous with destination card FPDP RECEIVER SOURCE CARD FPDP TRANSMITTER DESTINATION CARD FPDP IN FPDP RM or R FPDP OUT FPDP TM FPDP INTERFACE SOURCE CARD LINK INTERFACE LINK INTERFACE DESTINATION CARD FPDP INTERFACE FLOW CONTROL DATA Figure 11 2 FPDP and SL240 Terminology 11 4 CMC Mating Conn...

Page 103: ...PRESENT_L ADS_L WEN_L REN_L INT_L SEL_L AD 15 0 MCLK CFG 1 0 If a microcontroller is not used the microcontroller specific signals should be handled as shown below MCU_PRESENT_L Tie to 3 3 V through a 10k resistor ADS_L Tie to 3 3 V through a 10k resistor WEN_L Tie to 3 3 V through a 10k resistor REN_L Tie to 3 3 V through a 10k resistor INT_L Ignore This is an output SEL_L Tie to 3 3 V through a ...

Page 104: ..._IN B30 N C N C A31 PECL_IN B32 GND A33 GND B34 N C N C A35 N C N C B36 N C N C A37 N C N C B38 GND A39 3 3 V B40 N C N C A41 SEL B42 INT A43 MCU_PRESENT B44 GND A45 GND B46 REN A47 RESERVED B48 WEN A49 CRC_EN B50 GND A51 GND B52 ADS A53 CLK_CFG0 B54 MCLK A55 CLK_CFG1 B56 GND A57 3 3 V B58 CFG0 A59 IGNORE_FC B60 CFG1 A61 CONVERT_SYNC B62 GND A63 GND B64 RESERVED Certain signals are important for t...

Page 105: ... SL100 SL240 CMC register set AD 9 8 CMC Register Bits Accessed 00 7 0 01 15 8 10 23 16 11 31 24 When a register read is performed AD 15 8 00000000 is read back For register reads writes the register bits are shown in AD 7 0 in the following bit order 31 24 23 26 15 8 7 0 This does not mean the most significant byte must be accessed first and the least significant byte must be accessed last The by...

Page 106: ...is only retained for compatibility with older third part devices Both nodes on the link or all nodes in a loop configuration should be set to a common CRC mode or the resulting mismatch will cause data errors and or link errors IGNORE_FC Input Ignore Flow Control If MCU_PRESENT is asserted this value is ignored and the internal register value is used Set to 1 to ignore flow control from the remote...

Page 107: ...0 to use configuration signals from the microcontroller interface Set to 1 to use configuration signals from the P3 connector REN Input Read Enable microcontroller read enable See section 11 9 microcontroller Interface for details WEN Input Write Enable microcontroller write enable See section 11 9 microcontroller Interface for details SEL Input microcontroller Select microcontroller select See se...

Page 108: ...ot propagate through the Transmit FIFO within the SL100 SL240 CMC card and thus cannot be directly associated with the corresponding data Their use is not affected by the state of the Disable Transmitter bit in the Link Control register Thus RDIR PIO1_IN PIO2_IN and TNRDY are transmitted onto the link regardless of if the transmission of link data is enabled In non loop operation LWRAP 0 in the Li...

Page 109: ... Receive FIFO 8B 10B Encoder Transmit FIFO Fiber Input Fiber Output Disable Receiver note CMC Connectors LWRAP note TDIR RNRDY PIO1_OUT PIO2_OUT RDIR TNRDY 1 0 1 0 1 0 RD 31 0 TD 31 0 NOTE These bits are located in the Link Control register Figure 11 3 Signal Flow of PIO1 PIO2 DIR and NRDY Through an SL100 SL240 CMC Card ...

Page 110: ...A29 RD26 B30 RD25 A31 GND B32 RD24 A33 RD23 B34 RD22 A35 RD21 B36 GND A37 RD20 B38 RD19 A39 5 V B40 RD18 A41 RD17 B42 RD16 A43 RD15 B44 GND A45 RD14 B46 RD13 A47 GND B48 RD12 A49 RD11 B50 RD10 A51 RD9 B52 5 V A53 RD8 B54 RD7 A55 GND B56 RD6 A57 RD5 B58 RD4 A59 RD3 B60 GND A61 RD2 B62 RD1 A63 5 V B64 RD0 These signals are common on the P4 and P6 connectors Certain signals are important for the tran...

Page 111: ...peration PIO1_OUT Output Programmable I O 1 This is a user defined output that is removed from the data stream at the decoder interface This output line is shared with the FPDP transmitter interface P4 See note 2 for additional information on its operation PIO2_OUT Output Programmable I O 2 This is a user defined output that is removed from the data stream at the decoder interface This output line...

Page 112: ...2 words of data in each frame with an overhead of up to nine ordered sets The reference clock is typically driven by an on board oscillator The standard reference clock frequency for SL100 is 53 125 MHz while the standard reference clock frequency for SL240 is 125 MHz These signals do not propagate through the Transmit FIFO within the SL100 SL240 CMC card and thus cannot be directly associated wit...

Page 113: ...ith the corresponding data Their use is not affected by the state of the Disable Receiver bit in the Link Control register Thus TDIR PIO1_OUT PIO2_OUT and RNRDY are received from the link regardless of if the reception of link data is enabled PIO1_IN PIO2_IN 8B 10B Decoder Receive FIFO 8B 10B Encoder Transmit FIFO Fiber Input Fiber Output Disable Receiver note CMC Connectors LWRAP note TDIR RNRDY ...

Page 114: ...B16 TD10 A17 GND B18 GND A19 TD11 B20 TD12 A21 TD13 B22 TD14 A23 TD15 B24 TD16 A25 TD17 B26 TD18 A27 TD19 B28 GND A29 5 V B30 5 V A31 TD20 B32 TD21 A33 TD22 B34 TD23 A35 GND B36 TD24 A37 GND B38 TD25 A39 TD26 B40 TD27 A41 TD28 B42 GND A43 GND B44 TD29 A45 TERROR B46 TD30 A47 RESET B48 TD31 A49 5 V B50 PIO2_OUT A51 TSYNC B52 GND A53 TDIR B54 5 V A55 TDVALID B56 PIO2_IN A57 TSUSPEND B58 PIO1_OUT A59...

Page 115: ... FIFO if an error is detected There is no real indication where the error occurred TNRDY Input Transmit Not Ready Set to 0 to tell the FPDP interface that the FPDP receiver is not ready to accept data yet This signal is encoded and sent over the link interface Set to 1 to tell the FPDP interface that the FPDP receiver is ready to accept data See note 1 for additional information on its operation P...

Page 116: ... a 0 when a TSYNC is clocked out of the Receive FIFO Otherwise it is a 1 The transmitter at the remote end determines if TSYNC with TDVALID or TSYNC without TDVALID is sent 11 5 Programmed Inputs Outputs PIOs The PIO1_IN PIO2_IN and RESET inputs to the rehostable CMC FPDP card are shared between the transmit P4 and receive P6 interfaces These signals should always be driven from the same source to...

Page 117: ...tolerant 3 3 V signaling interface Table 11 8 lists some of the electrical parameters for this interface Table 11 8 DC Characteristics Parameter Description Min Max Units VIH Input High Voltage 2 0 5 5 V VIL Input Low Voltage 0 5 0 8 V II Input Leakage Current 10 10 µA VOH Output High Voltage 2 4 3 3 V VOL Output Low Voltage 0 4 V IOH Output High Current 24 mA IOL Output Low Current 24 mA The powe...

Page 118: ...9 and Table 11 10 Table 11 9 Source Card AC Characteristics Signal Min Max Units Receiver STROBE 70 MHz Data D 31 0 setup 5 ns DVALID setup 5 ns SYNC setup 5 ns Table 11 10 Destination Card AC Characteristics Signal Min Max Units Data D 31 0 clock to out 9 ns DVALID clock to out 9 ns SYNC clock to out 9 ns NOTE The delay listed in the destination card characteristics is the clock to out delay of t...

Page 119: ...a few of these transactions In addition to this appendix see Appendix F FPDP Primer for details about these signals VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID XXXX XXXX XXXX DVALID D 31 0 SYNC XXXX VALID SUSPEND D 31 0 DVALID STROBE VALID VALID VALID VALID VALID XXXX VALID VALID XXXX XXXX VALID VALID VALID NRDY STROBE 1 2 4 3 Figure 11 7 Parallel FPDP Interface Timing Diagram ...

Page 120: ...iring a full PCI bus This bus only has one valid configuration defined which is designed for 8 bit microcontrollers and PLDs The register map in Appendix B contains the contents and offsets of these registers Burst operations are not permitted on this interface To read from the registers three clock cycles are needed The first clock cycle is used to transfer the address to the CMC card The second ...

Page 121: ...nd is left unused to remain consistent with the read operation On the third clock the data is actually written to the register Note that all of the registers in the interface are 32 bit registers and the other 24 bits written to the register on a write operation are the current read values for those bits Figure 11 9 shows a single write to the registers XX XX ADDR XXXXXXXX XXXXXXXX DATA XXXXXXXX M...

Page 122: ......

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