REGISTER SET
Copyright 2012
6-1
FibreXtreme HW Reference for FPDP Cards
6.1 Overview
The PCI FibreXtreme Carrier and SL240 rehostable CMC FPDP cards are designed so
configuring the cards is as simple as possible. With minimal configuration, an SL240
FPDP card can transfer data between the link interface and the FPDP interface. This
section describes the register set bit definitions.
These definitions apply to the Access column shown in the following tables:
•
R/W – Readable/Writable bit.
•
R/WOC – Readable/Write One Clear bit.
•
W – Write-only bit.
•
R – Read-only bit.
•
None – Do not read or write to this bit.
6.1.1 Interrupt CSR (INT_CSR) – Offset 0x00
NOTE:
Do not write a ‘1’ to bit 20, Enable Link Error Interrupt, of the Interrupt CSR
register. With the current revision of firmware, this resets the microcontroller on the
PCI FibreXtreme Carrier card, and causes the active register configuration to be
reloaded from the EEPROM. This may be fixed in a future firmware revision and these
bits will work as described in this manual.
Bit
Description
Access
Reset
Value
3 to 0
Reserved
None
0
4
Link Error Interrupt – A ‘1’ indicates active, a ‘0’
indicates not active. Write ‘1’ to clear.
R/WOC
0
5
FPDP Interrupt – A ‘1’ indicates active, a ‘0’ indicates
not active. Write ‘1’ to clear.
R/WOC
0
6
Threshold Interrupt – A ‘1’ indicates active, a ‘0’
indicates not active. Write ‘1’ to clear.
R/WOC
0
7
Reserved
None
0
19 to 8
Reserved
None
0
20
Enable Link Error Interrupt – Set to ‘1’ to enable
interrupts, set to ‘0’ to disable interrupts.
R/W
0
21
Enable FPDP Interrupt – Set to ‘1’ to enable interrupts,
set to ‘0’ to disable interrupts
R/W
0
22
Enable Threshold Interrupt – Set to ‘1’ to enable
interrupts, set to ‘0’ to disable interrupts
R/W
0
23
Reserved
None
0
31 to 24
Reserved
None
0