REGISTER SET
Copyright 2012
6-2
FibreXtreme HW Reference for FPDP Cards
6.1.2 Board CSR (BRD_CSR) – Offset 0x04
Bit
Description
Access
Reset
Value
0
Reserved
None
0
1
Reset – Write ‘1’ to reset the card. Writing ‘0’ has no
affect.
W
0
2
Reserved
None
0
3
JTAG TCK# – Controls the TCK# line on the JTAG
port.
R/W
0
4
JTAG TMS# – Controls the TMS# line on the JTAG
port.
R/W
0
5
JTAG TDO# – Controls the TDO# line on the JTAG
port.
R/W
0
6
JTAG TDI# - TDI# line from the JTAG port.
R
1
7
JTAG Enable – Enable the JTAG port on the FPGA.
R/W
0
14 to 8
Revision ID – Revision level of the card controller.
R
See
desc.
15
SL100/SL240 – A ‘1’ indicates this is an SL240 card, a
‘0’ indicates this is an SL100 card.
R
See
desc.
23 to 16
Extended Revision ID – These bits are used to identify
intermediate or special firmware revisions. Bit 23 = ‘0’
indicates the Copy Master Mode bit in the Link Control
register is ‘0’ after a card reset. Bit 23 = ‘1’ indicates
the Copy Master Mode bit in the Link Control register is
‘1’ after a card reset.
R
See
desc.
31 to 24
Reserved
None
0
