REHOSTABLE CMC FPDP INTERFACE
Copyright 2012
11-20
FibreXtreme HW Reference for FPDP Cards
Table 11-11 FPDP Transmitter Interface Timing Parameters
Parameter
Description
Min
Max
1
Data,
/DVALID
,
/SYNC
setup time
5 ns
---
2
Data,
/DVALID
,
/SYNC
hold
time
0 ns
---
3
/SUSPEND
asserted to data
stop
---
16 clocks
4
/SUSPEND
de-asserted to
data started
1 clock
---
11.9 Microcontroller Interface
The microcontroller interface on the SL240 CMC card is used to access the internal
control and status registers. This provides the same flexibility as the PCI based cards, but
without actually requiring a full PCI bus. This bus only has one valid configuration
defined, which is designed for 8-bit microcontrollers and PLDs. The register map in
Appendix B contains the contents and offsets of these registers. Burst operations are not
permitted on this interface.
To read from the registers, three clock cycles are needed. The first clock cycle is used to
transfer the address to the CMC card. The second clock cycle is used as a turn-around
cycle for the bus, since it can be driven from bi-directional bus interfaces. On the third
clock cycle, the data is actually transferred back to the initiator. Figure 11-8 shows a
single read from the registers.
XX..XX ADDR XXXXXXXX
XXXXXXXX DATA XXXXXXXX
MCLK
/ADS
/WEN
/REN
/SEL
AD[15:8]
AD[7:0]
Figure 11-8 Microcontroller Single Read