Curtiss-Wright FHK4-FM4MWB04-00, Hardware Reference Manual

Page: 104 / 123

REHOSTABLE CMC FPDP INTERFACE
Copyright 2012 11-4 FibreXtreme HW Reference for FPDP Cards
Table 11-2 FPDP Configuration Interface (P3)
Pin
Input
Lines
Output
Lines Pin
Input
Lines
Output
Lines
A1 AD0 AD0 B2 GND
A3 GND B4 AD1 AD1
A5 AD2 AD2 B6 AD3 AD3
A7 AD4 AD4 B8 GND
A9 +3.3 V B10 AD5 AD5
A11 AD6 AD6 B12 AD7 AD7
A13 AD8 B14 GND
A15 GND B16 AD9
A17 AD10 B18 AD11
A19 AD12 B20 GND
A21 +3.3 V B22 AD13
A23 AD14 B24 AD15
A25 N.C. N.C. B26 GND
A27 GND B28 N.C N.C.
A29 PECL_IN B30 N.C N.C.
A31 /PECL_IN B32 GND
A33 GND B34 N.C N.C.
A35 N.C. N.C. B36 N.C. N.C.
A37 N.C. N.C. B38 GND
A39 +3.3 V B40 N.C. N.C.
A41 /SEL B42 /INT
A43 /MCU_PRESENT B44 GND
A45 GND B46 /REN
A47 RESERVED B48 /WEN
A49 CRC_EN B50 GND
A51 GND B52 /ADS
A53 CLK_CFG0 B54 MCLK
A55 CLK_CFG1 B56 GND
A57 +3.3 V B58 CFG0
A59 IGNORE_FC B60 CFG1
A61 CONVERT_SYNC B62 GND
A63 GND B64 RESERVED
Certain signals are important for the transmitter interface, while others are important only
for the receive interface. In the following signal descriptions, a ‘1’ refers to a logic high
level (above 2.0 V), while a ‘0’ refers to a logic low level (less than 0.8 V). All signals
use the LVTTL Input/Output standard.