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CSS Laboratories
Section 4 – Technical References
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34
Memory Configuration
The following chart shows all possible memory configurations for the SBP-205.
SBP-205 Memory Configuration
RAM
Bank 0
Bank 1
RAM
Bank 0
Bank 1
64 MB
8M x 64/72
256 MB
32M x 64/72
128 MB
8M x 64/72
8M x 64/72
320 MB
32M x 64/72
8M x 64/72
128 MB
16M x 64/72
384 MB
16M x 64/72
32M x 64/72
192 MB
16M x 64/72
8M x 64/72
512 MB
32M x 64/72
32M x 64/72
256 MB
16M x 64/72
16M x 64/72
System Interrupt Chart
The processor has 2 controllers that supply a total of 16 IRQs. The following chart
shows IRQ assignments in order of decreasing priority.
System Interrupts
IRQ
Function
NMI Parity
error
IRQ0
Reserved, interval timer
IRQ1
Reserved, keyboard buffer full
IRQ2
Reserve, cascade interrupt from slave PIC
IRQ3
Onboard serial port 2
IRQ4
Onboard serial port 1
IRQ5 User
available
IRQ6 Onboard
floppy
controller
IRQ7 Onboard
parallel
port
IRQ8 Real-time
clock
(RTC)
IRQ9 User
available
IRQ10 User
available
IRQ11 User
available
IRQ12
Onboard mouse port if enabled, else user available
IRQ13
Reserved, math coprocessor
IRQ14
Onboard primary IDE disk controller
IRQ15
Onboard secondary IDE disk controller
