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CSS Laboratories
Section 4 – Technical References
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Section 4 – Technical References
SBP-205 General Specifications
Form factor
13.28” x 7.25”
CPU
Single Intel Pentium II/III:
Host bus frequencies of 66/100/133 MHz
Up to 1 GHz
Cache
An external 64-bit wide non-blocking second level (L2) cache, supporting 256K or
512K running at full CPU speed is inside the CPU.
Memory Subsystem
On-board 64-bit path memory:
Two (2) 168-pin DIMM sockets. Each socket provides one bank of memory
Up to 512 MB total memory (2 x 256MB)
Either standard SDRAM or PC-133 SDRAM
ECC supported.
Bus Interface
ISA and PCI Local Bus compatible.
PCI Local Bus Interface
Fully compliant with the PCI Local Bus 2.1 specifications.
Optimized to allow the CPU to sustain the highest possible bandwidth (greater
than 100MB/sec sustained) and low latency of the PCI Bus.
Supports 4 PCI masters, pipeline snoop ahead and improved PCI to DRAM
write-back policy.
Data Path
64-bit Data/Memory
16 bit ISA
32-bit PCI
Interrupts
11 edge sensitive and configurable
4-PCI level sensitive
Mapped as any unused IRQ, configurable.
Fully Plug-and-Play compatible.
