6-12 Memory Configuration and BIOS Settings
EDO RASx# Wait
State
Sets the EDO DRAM RAS MA (memory address
bus) timing control type. Select either 1 or 2.
SDRAM
RAS-to-CAS Delay
When SDRAM is refreshed, both rows and
columns are addressed separately. This item
allows you to determine the timing of the
transition from Row Address Strobe (RAS) to
Column Address Strobe (CAS). The setting can
be 3 or 2.
SDRAM RAS
Precharge Time
Sets the SDRAM RAS Precharge Timing.
SDRAM must continually be refreshed or it will
lose its data. Normally, SDRAM is refreshed
entirely as the result of a single request. This item
allows you to specify the number of CPU clocks
allocated for Row Address Strobe to accumulate
its charge before the SDRAM is refreshed. If
amount of time specified is insufficient, SDRAM
refresh may be incomplete and data may be lost.
The setting can be 3 CLKs or 2 CLKs.
SDRAM CAS
Latency Time
Sets the CAS latency time to HCLKS of 2 or 3.
The value for this setting should have been
selected already based on the specifications of the
installed SDRAM. Do not change it unless the
specifications of the installed SDRAM or the
CPU have changed.
DRAM Data Integrity
Mode
Allows the user to set DRAM Data Integrity
mode to ECC (Error Checking and Correcting) or
Non-ECC. The ECC setting allows detection of
single-bit and multiple-bit errors, and recovery of
single-bit errors. The Non-ECC setting enables
byte-wide write capability but has no provision
for protecting data integrity in the DRAM array.
System BIOS
Cacheable
Allows the user to specify the system BIOS
F000-FFF area as cacheable or non-cacheable.
The Enabled setting yield better performance but
poses the danger of system errors if programs are
written to this memory area.
Table 6-6:
The Chipset Features Setup Screen items.
Item
Description