Copyright
©
2016
congatec
AG
TR33m10
68/105
Bus Number (hex)
Device Number (hex)
Function Number (hex)
PCI Interrupt
Routing
Description
00h
08h
00h
Internal
AMD PSP Controller
00h
09h
00h
N.A
AMD Audio Controller Host Bridge
00h
09h
02h
Internal
AMD Audio Controller
00h
10h
00h
Internal
XHCI Host Controller
00h
11h
00h
Internal
Serial ATA Controller
00h
12h
00h
Internal
EHCI Host Controller
00h
14h
00h
N.A.
SMBus Host Controller
00h
14h
03h
N.A.
PCI to LPC Bridge
00h
14h
07h
Internal
SD Controller
00h
18h
00h
N.A.
Chipset Configuration Registers
00h
18h
01h
N.A.
Chipset Configuration Registers
00h
18h
02h
N.A.
Chipset Configuration Registers
00h
18h
03h
N.A.
Chipset Configuration Registers
00h
18h
04h
N.A.
Chipset Configuration Registers
00h
18h
05h
N.A.
Chipset Configuration Registers
01h (see Note 3)
00h
00h
Internal
Onboard Gigabit LAN Controller
02h (see Note 3)
00h
00h
Internal
PCI Express Port 0
03h (see Note 3)
00h
00h
Internal
PCI Express Port 1
04h (see Note 3)
00h
00h
Internal
PCI Express Port 2
05h (see Note 3)
00h
00h
Internal
PCI Express Port 3
06h (see Note 3)
00h
00h
Internal
PCI Express Graphics Port 0
07h (see Note 3)
00h
00h
Internal
PCI Express Graphics Port 1
Note
1. The PCI Express Ports may only be visible if the PCI Express Port is set to “Enabled” in the BIOS setup program and a device is attached
to the corresponding PCI Express port on the carrier board.
2. The PCI Express Graphics Ports may only be visible if the PCI Express Graphics Port is set to “Enabled” in the BIOS setup program and a
device is attached to the corresponding PCI Express port on the carrier board.
3. The above table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board. The
given bus numbers will change based on actual hardware configuration.
