Concurrent Technologies VP 110/01 Series, Technical Reference Manual

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9.4 PCI Bus Resource Management
The local bus structure of the VP 110/01x is quite complex, and is based around two
independent PCI busses. In some cases the user may need to understand this structure and in
particular how the PC BIOS firmware allocates addresses and interrupt signals to the available
hardware resources. The following sections outline this allocation process and provide further
details of the PCI bus configuration.
There are two on-board PCI busses: a 64-bit bus which connects to the PMC site and the PMC
expansion sockets, and a second 32-bit bus which connects to the remaining on-board
peripherals (Ethernet, VME). Associated with these busses are a number of interrupt lines. The
64-bit bus is configurable for 5V or 3.3V switching levels (see Section 2.8) and can support
33MHz or 66MHz devices. The 32-bit bus operates at 33MHz only.
9.4.1 PCI Resource Allocation
The PC BIOS initializes all devices on the local PCI bus, and allocates appropriate memory
address ranges, I/O address ranges, and interrupt routings for all these devices. This process is
automatic as part of the BIOS “Plug-and-play” setup. Devices on the VME bus may also have
memory, I/O or interrupt resources, but these are not configured by the PC BIOS. Only four PCI
bus interrupt request lines are available, and must be shared between both the on-board PCI
bus devices and any Universe II VME bus interrupts. The ServerWorks chipset allows for a
flexible allocation of many PCI bus interrupts to the available interrupt inputs on the
PC-compatible interrupt controllers provided on the board. The PC BIOS uses this feature to
program default settings which it considers appropriate for the combination of on-board devices
and any device fitted to the PMC site. In some configurations, depending on the operating
system being used and the capability of the relevant device drivers, it may be necessary for the
user to modify this default configuration, to minimize the sharing of interrupt lines. The PC BIOS
Setup screen for Advanced | PCI Device Configuration allows this.
This screen allows the user to override the PC BIOS default selections for interrupt allocation,
but care must be taken when doing this to avoid conflicts which may result in operating system
or even BIOS “crashes”. To allow maximum flexibility of choice for the user, the PC BIOS
performs limited checks on the user’s interrupt allocation. In the event that there is a problem, it
may be necessary to clear the CMOS memory (see Section 2.7), or even to reset the Extended
System Configuration Data via the Reset Configuration Data field of the BIOS Setup
screen for Advanced configuration settings. The PC BIOS does not allow the user to override
the allocation of memory and I/O address ranges.
NOTE When reallocating interrupts using the BIOS Setup screens, try to avoid allocating
the PMC interrupts to ones also allocated to other devices. This sharing of
interrupts can cause problems with some operating systems where device drivers
do not correctly handle shared interrupts.
PC BIOS
VP 110/01x 9-5