Concurrent Technologies VP 110/01 Series Technical Reference Manual Download

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8.9

Port 80

A header has been provided for monitoring data written to I/O Port 80. The PC BIOS writes

status bytes to Port 80 that indicate a boot progress status and/or highlight any faults found.

Data written to this port can be monitored using a Logic State Analyzer (LSA) or seven segment

hexadecimal displays. See Section A.5.11 for details of the connector used for this port.
After boot-up this port can be used to monitor other status bytes written to Port 80, which can be

useful for debug purposes.

8-20

VP 110/01x

Additional Local I/O Functions

Summary of Contents for VP 110/01 Series

Page 1: ...4 Rev 02 August 2002 E mail info gocct com http www gocct com Concurrent Technologies Inc 3840 Packard Road Suite 130 Ann Arbor MI 48108 USA Tel 734 971 6309 Fax 734 971 6350 Concurrent Technologies Plc 4 Gilberd Court Newcomen Way Colchester Essex CO4 9WN United Kingdom Tel 44 1206 752626 Fax 44 1206 751116 ...

Page 2: ... result from its use In particular no license is either granted or implied under any patent or patent rights belonging to Concurrent Technologies Some parts of this document are reproduced with the permission of and remain copyright Phoenix Technologies Ltd 1997 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Concurrent Technolo...

Page 3: ...mmable Read Only Memory FSB Front Side Bus ISA Industry Standard Architecture LDT Long Duration Timer LFM Linear Feet per Minute LPC Low Pin Count NMI Non Maskable Interrupt PCI Peripheral Component Interconnect PIT Programmable Interval Timer PMC PCI Mezzanine Card POST Power on Self Test RFU Reserved for Future Use RTC Real Time Clock SCC Serial Communications Controller SCSI Small Computer Syst...

Page 4: ... Notes provide general additional information WARNING Warnings provide indication of board malfunction if they are not observed CAUTION Cautions provide indications of board or system damage if they are not observed iv VP 110 01x ...

Page 5: ...Revision Revision History Date 01 Initial Release July 2002 02 Added clarifications to several sections August 2002 VP 110 01x v ...

Page 6: ...n 2 4 2 4 2 POST LED P Yellow 2 4 2 4 3 Ethernet Speed LEDs Speed Yellow 2 4 2 4 4 Link Activity LEDs LK ACT Green 2 4 2 4 5 Battery Status LED B Yellow optional 2 4 2 4 6 Reset NMI Switch 2 4 2 4 7 External Reset 2 5 2 5 Installation of On Board Mass Storage 2 6 2 5 1 Hard Disk Storage Kit AD CP1 DR1 2 7 2 5 2 CompactFlash Storage Kit AD 200 001 2 8 2 6 Adding or Replacing DRAM Modules 2 9 2 7 In...

Page 7: ...ontrol Register I O address 214h 8 7 8 4 2 Watchdog Configuration 8 8 8 4 3 Using the Watchdog 8 8 8 4 4 Programming the Watchdog 8 9 8 5 Status Control Register 4 I O address 215h 8 11 8 6 Memory Page and Status Register I O address 216h 8 12 8 7 Status Control Register 3 I O address 217h 8 13 8 8 Long Duration Timer Periodic Interrupt Timer 8 14 8 8 1 Long Duration Timer Periodic Interrupt Timer...

Page 8: ...Test 28 SCC Interrupt Test 11 7 11 2 17 Test 29 SCC Internal Loopback Test 11 7 11 2 18 Test 30 SCC External Loopback 11 7 11 2 19 Test 33 Universe PCI VME Test 11 7 11 2 20 Test 34 Universe PCI Config Utility 11 8 11 2 21 Test 35 Universe VME Config Utility 11 8 11 2 22 Test 36 VME Bus Byte Swapping 11 8 11 2 23 Test 37 Bus Error Detection Test 11 9 11 2 23 1 Sub Test 1 VME Bus Error Detection by...

Page 9: ...1 25 11 2 44 Test 105 Interconnect Read Utility 11 25 11 2 45 Test 106 Interconnect Write Utility 11 25 11 2 46 Test 107 Cache Control Utility 11 26 11 2 47 Test 120 PCI Configuration Utility 11 26 11 2 48 Test 121 PCI Read Utility 11 27 11 2 49 Test 122 PCI Write Utility 11 27 11 2 50 Test 126 Display Board Configuration 11 27 11 2 51 Test 127 Retrieve BIST Information 11 27 A Specifications A 1 ...

Page 10: ...B 2 B 3 2 Pin out Tables B 2 B 4 AD VP2 004 20 B 3 B 4 1 Layout B 3 B 4 2 Pin out Tables B 3 B 5 AD VP2 005 00 B 4 B 5 1 Layout B 4 B 5 2 Pin out Tables B 4 B 6 Header Connector Configuration Tables B 5 x VP 110 01x ...

Page 11: ... 2 12 Figure 2 10 PMC V I O Jumper 2 13 Figure 6 1 Console Mode Switch 6 1 Figure 7 1 Memory Map 7 1 Figure 7 2 Flash Program Jumper 7 4 Figure 7 3 SRAM Backup Power Jumper 7 5 Figure 8 1 Watchdog Timer Switch 8 6 Figure 9 1 Mode Switch 9 1 Figure A 1 Connector Layout A 3 Figure A 2 Front Panel Connectors A 3 Figure A 3 Keyboard and Mouse Header LK1 Polarization A 7 Figure A 4 Serial Port RJ45 Con...

Page 12: ... Pin outs A 9 Table A 8 On Board Mass Storage Option Interface Pin outs A 10 Table A 9 PMC J11 Connector Pin outs A 11 Table A 10 PMC J12 Connector Pin outs A 12 Table A 11 PMC J13 Connector Pin outs A 13 Table A 12 PMC J14 Connector Pin outs A 14 Table A 13 PMC J21 Connector Pin outs A 15 Table A 14 PMC J22 Connector Pin outs A 16 Table A 15 PMC J23 Connector Pin outs A 17 Table A 16 PMC J24 Conn...

Page 13: ...t for further details Further details of other board options are given in Section 1 3 References to the board in this document will use the name VP 110 01x unless they apply only to a specific variant in which case the full name will be used The information contained in this manual has been written to provide users with all the information necessary to configure install and use the VP 110 01x as p...

Page 14: ...to the Level 2 cache before a Level 1 cache request occurs This reduces latency resulting in improved performance 1 2 2 Cache Memories The Level 1 and Level 2 caches are both implemented on the processor die for maximum performance The Level 1 cache is 32 Kbytes in size and the Level 2 cache is 512 Kbytes The Level 1 cache is organized as 4 way set associative with a 32 byte line size It is split ...

Page 15: ... page and memory type are selected via dedicated registers 1 2 8 Application Flash EPROM Intel StrataFlash memory is provided for use by application software and has capacities from 16 Mbytes to 64 Mbytes The memory is connected to the CSB5 X Bus interface and is accessible via a paged 512 Kbyte window This window is shared with the battery backed SRAM the page and memory type being selected via d...

Page 16: ... 1 of the Super I O Controller providing a 16550 compatible Serial Communications Controller The baud rate clock is generated internally by the Super I O Controller 1 2 16 Keyboard Mouse PS 2 type keyboard and mouse interfaces are available via an on board header See Section 6 2 for more information about these ports 1 2 17 Real Time Clock RTC A battery backed RTC device provides PC AT clock calen...

Page 17: ...g information The VP 110 01x board may be ordered with one of a few different VME P2 and P0 connector breakout or adapter modules Appendix B gives details of all these breakout modules Table 1 1 summarizes the interfaces available using each of these VME P2 breakouts Breakout VME P2 Connector Pins EIDE Floppy USB PMC Site 1 Rear I O P2 PMC Site 2 Rear I O P0 AD VP2 004 10 96 4 AD VP2 004 20 160 4 ...

Page 18: ...This page has been left intentionally blank 1 6 VP 110 01x Introduction and Overview ...

Page 19: ...ostatic discharge The list below outlines the steps necessary to configure and install the board Each entry in the list refers to a section in this chapter which will provide more details of that stage of the procedure 1 Unpack the board see Section 2 2 2 Check the board jumper and switch settings match the required operating mode see Section 2 3 3 Locate the board s indicators and switches see Se...

Page 20: ...aging is badly damaged or water stained the user must insist on the carrier s agent being present when the board is unpacked Once unpacked the board should be inspected carefully for physical damage loose components etc In the event of the board arriving at the customer s premises in an obviously damaged condition Concurrent Technologies or its authorized agent should be notified immediately 2 2 V...

Page 21: ...r LK4 PMC V I O 5V Normal Enabled Battery Section 2 8 Section 2 7 Section 7 4 Section 7 3 VGA Console Mode Mode BIOS User Switch 1 Watchdog Disabled 1 2 3 4 Section 2 4 6 1 2 3 4 Front Panel Switch Function Reset Not Used Section 9 1 Section 8 1 Section 8 4 Section 6 1 6 2 Figure 2 1 Default Jumper and Switch Settings ...

Page 22: ...aces as follows l Off 10 Mbits s l Steady On 100 Mbits s 2 4 4 Link Activity LEDs LK ACT Green These LEDs light when connection has been made on the corresponding Ethernet interface They will flash to indicate link activity and during periods of high Ethernet activity the LEDs may switch off for several seconds 2 4 5 Battery Status LED B Yellow optional This LED lights if the on board battery volt...

Page 23: ...rted 2 4 7 External Reset The External Reset input is also available on a front panel connector This will cause a board reset in the same way as the front panel switch This input consists of two small sockets one for connection of the reset input and the other ground reference This input can be driven from an open collector TTL output or discrete transistor or normally open switch relay contacts T...

Page 24: ...The mass storage option plugs into the 44 way header S1 and is secured via screws and spacers using the four mounting holes as shown in Figure 2 4 below 2 6 VP 110 01x Hardware Installation Mass Storage Option Mounting Holes EIDE Header S1 Mass Storage Option Connector Outline of Mass Storage Option Figure 2 4 Mass Storage Connector and Fixing Holes ...

Page 25: ... the VP 110 01x 1 Plug the 50 way connector into the disk drive as shown in Figure 2 5 below note the orientation 2 Plug the 44 way header S1 note the orientation 3 Fix the disk drive into position using the four screws and spacers provided Do not over tighten the screws NOTE If the board is likely to be subjected to mechanical vibration a suitable thread lock compound applied to the screws should...

Page 26: ... likely to be subjected to mechanical vibration a suitable thread lock compound applied to the screws should be considered The CompactFlash sites are labeled CompactFlash 1 and CompactFlash 2 If a single CompactFlash card is fitted it should always go into site 1 Site 2 should be used only when two CompactFlash cards are fitted The CompactFlash card s may be retained in position by fitting short M...

Page 27: ... will accommodate SODIMMs of 256 Mbytes and 512 Mbytes capacities NOTE SODIMMs using 256Mbit DRAMs with 8K refresh are required Figure 2 7 shows shows the way in which SODIMMs are fitted or removed No other changes are necessary when a SODIMM is added or removed VP 110 01x 2 9 Hardware Installation SODIMM SODIMM Figure 2 7 DRAM Module Replacement ...

Page 28: ... least the VME 5V Standby supply available during the change In order to reset the battery monitoring circuitry the battery must be removed for at least 7 seconds and replaced Depending on the way in which the board is operated and stored battery life should be in excess of 2 years The life expectancy will fall if the battery is subjected to long periods at temperatures of 45o C or above It will a...

Page 29: ...up the board for an invalid configuration or in other fault conditions it may be useful to be able to reset the contents of the CMOS RAM and Real Time Clock In this case the CMOS Clear Jumper can be used To clear the CMOS RAM to a known state fit the CMOS Clear jumper and apply power When the board is next powered down remove the jumper otherwise CMOS RAM will again be reset See Section 7 4 for ad...

Page 30: ... configurations and how to fit the PMC module to the VP 110 01x board Figure 2 10 shows the location and settings for the PMC V I O jumper NOTE The PMC V I O voltage is determined by a combination of the PMC polarizing key position and the V I O Jumper The PMC V I O will be set for which ever gives the highest voltage setting It is recommended that the polarizing keys and the jumper are set for th...

Page 31: ...VP 110 01x 2 13 Hardware Installation LK4 PMC V I O or 3 3V key 5V V I O Key 3 3V V I O Key or 5V keys 5V 3 3V Figure 2 10 PMC V I O Jumper ...

Page 32: ...s neatly into the runners 3 Push the board into the card cage until the P0 P1 and P2 connectors are firmly located Use the ejector handles for the final push 4 Screw the ejector handle retaining bolts into the holes in the chassis 5 Connect the I O cables to the connectors on the board s front panel and fix in place with the connectors retaining screws 6 If using a Breakout Module install it at th...

Page 33: ...all on the target hardware will require a monitor and keyboard during installation even if they can subsequently be re configured to use only a serial terminal See Section 6 1 for details of how to configure the board for this option 3 Connect any additional modules and peripherals especially any mass storage devices 4 Connect the console device and power up the board Wait for the PC BIOS to sign ...

Page 34: ...om floppy disk requires no special steps other than to connect the drive using an appropriate cable To bootload from CD ROM use the following procedure 1 While the BIOS is running its memory test press the ESC key 2 Wait for the pop up boot device menu to be displayed 3 Select the CD ROM drive using the cursor keys then press the Enter key 3 2 VP 110 01x Software Installation ...

Page 35: ...ter to continue 4 Setup will continue and report that it is loading drivers for the appropriate mass storage devices Press Enter again to resume the normal Windows Setup sequence 5 Allow Windows Setup to continue with the normal setup procedure up to the point where Windows prompts to know if the computer will participate on a network 6 Select this computer will participate on a network then click...

Page 36: ...elect the Hardware tab and click the Device Manager button 6 On the Device Manager tree view double click the first Ethernet device located in the Other Devices branch 7 Click Reinstall Driver to start the Device Driver Wizard 8 Click the Next button when the Welcome screen is displayed 9 Choose the Search option and click the Next button 10 Select the Floppy disk drive option on the Locate Driver...

Page 37: ...ebooted login as the super user login name root 4 At the command prompt type netconfig and fill in the forms for network parameters appropriately for the network being used When this is complete reboot the operating system to enable the new settings 5 For full control of the system configuration use the linuxconf utility This is not installed by the RedHat installer but can be manually installed f...

Page 38: ...d on the target hardware Concurrent Technologies can supply on request a separate Board Support Package BSP for this board and many others Read the readme file provided with this package for details of how to configure and run VxWorks on the VP 110 01x board 3 6 VP 110 01x Software Installation ...

Page 39: ...ss Storage option kits In addition the Application Flash EPROM may be configured to operate as a ROM disk and the Battery Backed SRAM configured to operate as a RAM disk The order in which the PC BIOS firmware tries to bootload from these drives can be changed via the BIOS Setup screen for Boot 4 1 Floppy Disk Interface The floppy disk interface supports up to two drives of 360 Kbytes 720 Kbytes 1...

Page 40: ...ave drives The BIOS Setup screens for Main Secondary Master and Main Secondary Slave allow the user to see what is connected to this interface and to select some characteristics of the drives manually Note that when using faster EIDE drives the overall cable length from the PP 110 01x board to the drive furthest from the board must be kept as low as possible and in any case no more than 18 inches ...

Page 41: ...configured as a ROM disk it may also be configured as a boot device using the Boot Device Selection menu see Section 9 3 the original floppy Drive A will be promoted to Drive B but will no longer be bootable If Drive B has been configured as a RAM disk the original floppy Drive A will be further promoted to Drive C provided that there are no hard disk drives attached Software for generating and pr...

Page 42: ...de and data in a robust but easily accessible format that is also writeable without the need to erase and program flash memory Drive B may be configured as a RAM disk via the BIOS Setup screen Main ROM RAM Disk B The original floppy Drive B will no longer be accessible 4 4 VP 110 01x Mass Storage Interfaces ...

Page 43: ...troller for any combination of VME interrupts and can be an interrupter generating either a software interrupt or any of the Universe s internal interrupt sources on any IRQ level All VME interrupts are directly mapped between the Universe II registers and the VME bus backplane Of the PCI LINT lines only LINT0 is mapped into the PCI interrupt and with LINT1 mapped to NMI The Universe II device use...

Page 44: ... 15 8 D 15 8 D 23 16 D 7 0 D 31 24 The hardware decodes the VME transfer taking place to see if it is swappable checks to see if swapping is enabled and then configures a set of multiplexors to perform the required data swap For master and slave read cycles the byte swap hardware imposes negligible delay on the VME bus cycle since the decode and configuration occur before the data is valid For wri...

Page 45: ...Bus Error event may be detected by means of the Bus Error Interrupt or by polling the VME Address Capture status bit When using the Bus Error Interrupt with the VME Address Capture these functions must be enabled together and outside the monitored transfer This will permit both functions to detect the Bus Error event The VME Bus Error Interrupt does not have to be enabled for the VME Address Captu...

Page 46: ...ble 5 1 VME Address Capture Read Register The sequence will repeat for subsequent read accesses and is only readable after a bus error address capture The sequence will repeat for subsequent read accesses and is only readable after a bus error address capture Bits A31 A01 form the most significant 31 bits of the address which caused the bus error All these bits are valid even for A24 or A16 bus cy...

Page 47: ...isory program 0 0 1 1 1 1 0F A32 supervisory BLT 0 1 0 0 0 0 10 User defined 0 1 0 0 0 1 11 User defined 0 1 0 0 1 0 12 User defined 0 1 0 0 1 1 13 User defined 0 1 0 1 0 0 14 User defined 0 1 0 1 0 1 15 User defined 0 1 0 1 1 0 16 User defined 0 1 0 1 1 1 17 User defined 0 1 1 0 0 0 18 User defined 0 1 1 0 0 1 19 User defined 0 1 1 0 1 0 1A User defined 0 1 1 0 1 1 1B User defined 0 1 1 1 0 0 1C ...

Page 48: ...LT 1 1 1 1 0 1 3D A24 supervisory data 1 1 1 1 1 0 3E A24 supervisory program 1 1 1 1 1 1 3F A24 supervisory BLT Table 5 2 VME Address Modifier Codes Continued 5 4 2 VME Address Capture Control Register Write Only 7 6 5 4 3 2 1 0 ________ ________ _________ ________ _________ _________ _________ _________ RFU RFU RFU RFU RFU ABORT RESET ENABLE CAPTURE READ CAPTURE SEQUENCE Bit 0 Enable Capture 0 n...

Page 49: ...ce The serial line may be configured for speeds up to 115kbaud With some operating systems or in some applications it is preferable to use a serial terminal as an operator console device for the board In this case it will be necessary to configure the board for operation with a Serial Console When configured in this mode the PC BIOS firmware will re direct its output to the COM1 port and similarly...

Page 50: ... for the keyboard and mouse interfaces is protected by a 0 75A self resetting current limiting circuit To reset this circuit power the board off remove and replace the faulty keyboard or mouse device then power up again NOTE External devices that derive power from the keyboard mouse interface may be used provided that the total current taken by all devices is less than 0 75A 6 2 VP 110 01x Other I...

Page 51: ...EEE addresses which are identified by two labels fixed to the board Two LEDs are associated with each interface to indicate connection speed yellow LED and link activity green LED 100Mbit s connection is indicated by the speed LED lighting and link connection activity is denoted by the green LED lighting flashing See Section 2 4 for the location of these connectors and LEDs and further details of ...

Page 52: ...be powered by an additional Lithium battery when main power to the board is removed See Section 2 7 for more details of how to fit or replace the battery The Clock device also provides 256 bytes of CMOS RAM in which the PC BIOS keeps much of its setup screen data and other information 6 4 VP 110 01x Other Interfaces ...

Page 53: ... Serial Bus USB A single USB 1 0 interface is provided on this board and is accessed via the VME P2 connector or a Breakout Module This channel can operate at 1 5Mbits s or 12Mbits s Other Interfaces VP 110 01x 6 5 ...

Page 54: ...t LED Speaker The Power On Self Test POST LED is connected to the PC Speaker port The LED will light when the speaker port is driven The VP 110 01x is not fitted with an audio speaker output 6 6 VP 110 01x Other Interfaces ...

Page 55: ...ory provision is determined by suffixes to the part number VP 110 01x 7 1 FFFFFFFFh FFF80000h FFF00000h FFE00000h FFC00000h 00100000h 000A0000h 00000000h 512K BIOS VSA Flash EPROM 512K SRAM Strata Flash EPROM 2 Mbyte SRAM PCI Free Memory SDRAM up to 1024 Mbytes PC Shadow area and Graphics Memory SDRAM Unused Top of DRAM 512 to 1024 Mbytes Figure 7 1 Memory Map ...

Page 56: ...4 pin SODIMM site allows an additional 256 Mbytes or 512 Mbytes to be fitted either at the factory or in the field giving a maximum size of 1 Gbyte Section 2 6 describes how to fit this SODIMM and details the types supported The SDRAM can be accessed from both the local PCI bus and the VME backplane 7 2 VP 110 01x Memory ...

Page 57: ...and for the BIOS reprogramming information if you believe that such an update is required The second Flash EPROM part is soldered to the board and is used at the factory for test purposes It is currently reserved for future use by Concurrent Technologies The BIOS and Test Firmware EPROMs are co resident that is they occupy the same CPU address range A special purpose control bit is used to select ...

Page 58: ...type are selected via the Memory Page and Status register The specific device is selected via Status Control Register 4 The device selection gives access to each of up to four 16 Mbyte devices thus the first 16 Mbyte is device 0 and so forth The Application Flash EPROM may be write protected using a jumper shown in Figure 7 2 Write and erase cycles are permitted only when the jumper is in the Enab...

Page 59: ...e devices thus the first 16MB is device 0 and so forth An additional 2 Mbyte window is also provided specifically for SRAM to permit easy access to the entire 2 Mbytes space Refer to Figure 7 1 A jumper is provided see Figure 7 3 to disconnect the backup supply to the SRAM to extend the battery life for CMOS settings The jumper must be fitted to permit data retention When the board is installed in...

Page 60: ...This page has been left intentionally blank 7 6 VP 110 01x Memory ...

Page 61: ...Slave DMA Controller CSB5 LPC host 00F0h Math Coprocessor Error 0210 021Ch Control Status Registers LDT 03F0 03F7h Floppy Controller Super I O 03F8 03FFh COM1 Serial Super I O 04D0 04D1h Interrupt Control CSB5 0C00 0C01h Interrupt Address Index Redirection CSB5 0C06 0C08h Black Box CSB5 0C14h PCI Error Status CSB5 0C6Fh Flash EPROM Write Protect CSB5 0C50 0C51h Client Management Security CSB5 0CD6...

Page 62: ...egister 4 l 216h for Memory Page and Status Register l 217h for Status Control Register 3 l 218h for Long Duration Timer LS byte l 219h for Long Duration Timer Mid Low byte l 21Ah for Long Duration Timer Mid High byte l 21Bh for Long Duration Timer MS byte l 21Ch for Long Duration Timer Status Control Register NOTE The functions provided by the VME Address Capture Data Control registers are descri...

Page 63: ...ode the VME cycle type as it takes place to determine if swapping is possible It then configures a set of multiplexors to perform the swap To meet the VME bus timing specifications for write cycles it is necessary to delay the cycle while the multiplexors are configured Setting bit 5 of this register turns off the delay but should only be done if all VME cycles are guaranteed swappable Bit 6 User ...

Page 64: ...g a power on or reset Subsequent writes to this register will not affect this bit NOTE This feature is reserved for use by the BIOS only User software may read this bit to determine the operating frequency but may not change it Bit 5 Therm Alert Enable Read Write once 0 Therm Alert Disabled Default 1 Therm Alert Enabled This bit controls the logic that will turn the processor off if an over temper...

Page 65: ...Bus Error Flag Read Clear The flag is set by a bus error occurring during a cycle in which the Universe is the VME bus master The bit can be cleared by writing to the register with a zero in this bit position This should be done as part of the VME bus error interrupt routine 0 VME bus error has not occurred 1 VME bus error has occurred Bit 6 LINT1 from the Universe is the cause of NMI Read Only Th...

Page 66: ...gular intervals If it is not restarted for a period of approximately 1 second the timer will expire and cause a Non Maskable Interrupt or reset to the local processor See Section 8 4 3 for further details of watchdog timer operation The watchdog timer facility is provided by a Maxim MAX705 power on reset supervisor chip and additional hardware 8 6 VP 110 01x Additional Local I O Functions Switch 4...

Page 67: ... 3 Watchdog Status Read Only 0 Watchdog timed out 1 Watchdog OK This bit can be used to determine if the watchdog was the source of an NMI or reset A valid watchdog restart will set this bit to Watchdog OK if the watchdog had previously timed out Bit 4 Watchdog Enable Jumper Status Read Only 0 Watchdog is under software control 1 Watchdog disabled in hardware Bit 5 Watchdog Software Enable Read Wr...

Page 68: ...og the complement of the lower two bits needs to be written into the Watchdog Status Control register These two bits must also be the complement of each other i e 0 1 or 1 0 Writing any other value or the same value will not restart the watchdog If the watchdog time out is configured to generate a board reset and a time out occurs the watchdog circuit will also be reset The watchdog must be enable...

Page 69: ...02 define WD_PAT_2 0x01 define WD_ACTION_MASK 0x04 define WD_ACTION_NMI 0x00 define WD_ACTION_RST 0x04 define WD_STATUS 0x08 define WD_HW_DISABLE 0x10 define WD_SW_ENABLE 0x20 vEnableWatchdog configure the watchdog for NMI or RESET on timeout RETURNS none void vEnableWatchdog UINT8 bTimeoutAction action on timeout NMI or Reset UINT8 bTemp bTemp inbyte WATCHDOG_STATCTL bTemp WD_ACTION_MASK set watc...

Page 70: ...TL bTemp WD_PAT_1 vDisableWatchdog vPatWatchdog restart the watchdog to prevent timeout Bits 1 0 of the Watchdog status control register are inverted before writing back RETURNS none void vPatWatchdog void UINT8 bTemp UINT8 bPat bTemp inbyte WATCHDOG_STATCTL bPat bTemp WD_PAT_MASK get complement of bits 1 0 bTemp WD_PAT_MASK clear the bits 1 0 in data bTemp bPat set new bits outbyte WATCHDOG_STATC...

Page 71: ...CT 0 EREADY EREADY Bits 0 1 Select Flash Bank Read Write Bit 1 Bit 0 Bank Device 0 0 0 0 1 1 1 0 2 1 1 3 Bit 2 Backup Battery Status Read Only 0 Backup battery power is normal 1 Backup battery is below level for data retention Bits 5 3 Reserved Bit 6 PMC Site 1 Non Monarch Boot Status 0 Not ready 1 Ready Bit 7 PMC Site 2 Non Monarch Boot Status 0 Not ready 1 Ready VP 110 01x 8 11 Additional Local ...

Page 72: ...Flash and SRAM page select read write NOTE The Flash devices used are 128 Mbits 16 Mbytes using page bits 0 to 4 Up to four 16 Mbyte devices can be fitted and are selected via the bank select bits of Control and Status Register 4 Page bit 5 is unused Bit 6 Memory Select Read Write 0 Application Flash 1 Non Volatile SRAM Bit 7 Application Flash Program Status Read Only 0 Device ready 1 Device busy ...

Page 73: ...icate the state of the VME Geographic Address parity pin GAP of the VME P1 connector It will read as 1 if the board is installed in a backplane which does not support this signal Bit 6 VME System Reset Enable Read Only This bit controls the SYSRST input from the VME Bus 0 System Reset is disabled default 1 System Reset is enabled Bit 7 Mode Switch Read Only This bit is used to select the operating...

Page 74: ...4 3 2 1 5 1 0 75MHz LF Clock 32 768kHz NOTE 1 1MHz is selected by the BIOS as the default clock frequency SIO set to 4MHz as this is the clock frequency used on other Concurrent Technologies boards NOTE 2 Although the LFCLK can be configured to 1Hz it also drives other circuitry It is recommended that the LFCLK be left at 32 768kHz for future compatibility The clock mark space ratio can be any val...

Page 75: ...ister loads a value into the mid low byte of the LDT PIT counter The counter should be stopped when writing or the result will be indeterminate 8 8 3 Long Duration Timer Periodic Interrupt Timer Mid high Byte 7 6 5 4 3 2 1 0 ________ ________ _________ ________ _________ _________ _________ _________ LDT23 LDT22 LDT21 LDT20 LDT19 LDT18 LDT17 LDT16 Bits 7 0 Mid high Byte of LDT Read Write Reading t...

Page 76: ...PIT 2 000Hz 110 PIT 5 000Hz 111 PIT 10 000Hz All frequencies are with a 1MHz clock source selected via bits 6 and 5 Bit 4 LDT PIT Interrupt Flag Read Clear This bit is set if the LDT RUN bit is set AND either the LDT rolls over or the PIT interval expires This bit can be cleared by writing to the register with a zero in its bit position This should be done in the LDT PIT interrupt service routine ...

Page 77: ...fine TIMER_ROLLOVER 0x10U define MODE_MASK 0x0EU define MODE_PIT_10000Hz 0x0EU define MODE_PIT_5000Hz 0x0CU define MODE_PIT_2000Hz 0x0AU define MODE_PIT_1000Hz 0x08U define MODE_PIT_500Hz 0x06U define MODE_PIT_200Hz 0x04U define MODE_PIT_100Hz 0x02U define MODE_LDT 0x00U define MODE_RUN_MASK 0x01U define MODE_RUN_GO 0x01U define MODE_RUN_STOP 0x00U The following code fragment illustrates how a sim...

Page 78: ... to be volatile which prevents any C compilers which conform to the ANSI standard from optimizing accesses to the dCounter variable outbyte CONTROL_STATUS MODE_RUN_STOP outbyte TIMER_BYTE_0 0 outbyte TIMER_BYTE_1 0 outbyte TIMER_BYTE_2 0 outbyte TIMER_BYTE_3 0 outbyte CONTROL_STATUS MODE_PIT_100Hz MODE_RUN_GO dCounter 500 500 1 100 5 seconds install the interrupt for the PIT counter modify the PIC...

Page 79: ...dElapsedTime 1000000U dElapsedTime 1000000U The TIMER_BYTE_0 TIMER_BYTE_1 TIMER_BYTE_2 and TIMER_BYTE_3 control registers are at successive addresses and form a 32 bit register in little endian format It is possible to read and write the timer s value in a single 32 bit I O operation For example to read the timer s value the following C statement suffices DCounterValue inlong TIMER_BYTE_0 VP 110 0...

Page 80: ...light any faults found Data written to this port can be monitored using a Logic State Analyzer LSA or seven segment hexadecimal displays See Section A 5 11 for details of the connector used for this port After boot up this port can be used to monitor other status bytes written to Port 80 which can be useful for debug purposes 8 20 VP 110 01x Additional Local I O Functions ...

Page 81: ...and VSA mode a more flexible and comprehensive testing mode which can be used for system or board testing VSA mode operation and features are described in more detail in Chapters 10 and 11 of this manual Figure 9 1 shows the location of the switch on the board and its settings VSA mode may be exited either by operator command or by allowing the board to proceed through the VSA startup sequence wit...

Page 82: ...e used By default the serial line is programmed to operate at 9600 Baud with 8 data bits 1 stop bit and no parity 8N1 There is no flow control For fast terminals the baud rate can be increased via the Serial Console Baud Rate field of the Main Setup menu 9 2 VP 110 01x PC BIOS ...

Page 83: ...or some other problem This will be following by a prompt to the operator to press F1 to continue or F2 to enter Setup mode If no key is pressed within approximately five seconds the PC BIOS will continue with its normal startup sequence It will also re calculate the CMOS Checksum to prevent this error occurring again at a subsequent restart Pressing the F2 key at any time during the PC BIOS startu...

Page 84: ...heir BIOS Extension firmware to be enabled before they can be used as boot devices BIOS setup options are provided to control whether or not the board runs the BIOS Extensions for the Ethernet channels or the on board PMC sites The Option ROM Scan field of the appropriate device menu must be used to enable or disable the BIOS Extension The device menus are accessible from Ethernet channel 0 Advanc...

Page 85: ...for a flexible allocation of many PCI bus interrupts to the available interrupt inputs on the PC compatible interrupt controllers provided on the board The PC BIOS uses this feature to program default settings which it considers appropriate for the combination of on board devices and any device fitted to the PMC site In some configurations depending on the operating system being used and the capab...

Page 86: ...g the Setup screens When more than one PCI bus interrupt is routed to the same interrupt controller input that input will remain active while any of the sources connected to it are active PMC Expansion INTA PMC Expansion INTB PMC Expansion INTC PMC Expansion INTD PMC 1 INTA PMC 1 INTB PMC 1 INTC PMC 1 INTD PMC 2 INTA PMC 2 INTB PMC 2 INTC PMC 2 INTD Ethernet Channel 0 Ethernet Channel 1 Universe I...

Page 87: ... Function Code Device Description 0 0 0 Bridge to PCI bus 0 32 bits 0 0 1 Bridge to PCI bus 1 64 bits 0 4 0 Universe II 0 6 0 Ethernet channel 0 0 7 0 Ethernet channel 1 0 15 0 South Bridge 0 15 1 EIDE controller 0 15 2 USB controller 0 15 3 LPC bus controller 0 15 4 XIOAPIC0 interrupt controller 0 15 5 XIOAPIC1 interrupt controller 0 15 6 XIOAPIC2 interrupt controller 1 8 0 PMC site 1 primary fun...

Page 88: ...This page has been left intentionally blank 9 8 VP 110 01x PC BIOS ...

Page 89: ...er boards which lost the arbitration sequence will operate in a Slave Test Handler mode 10 2 1 Slot Numbering Throughout the VSA firmware boards are identified by their logical slot number This number does not represent the physical backplane slot The logical slot number is assigned by the Master Test Handler when it detects a board capable of participating in system testing Therefore boards from ...

Page 90: ... Tests BISTs 10 2 4 Remote Testing from the System Controller In a system comprising more than one Concurrent Technologies CPU board only the system controller board will provide a console interface however this board can be used to test the other VSA configured boards through their Slave Test Handlers During system startup the VSA configured system controller will detect all other functional VSA ...

Page 91: ...20 Test 20 has a command parameter BISTs may be executed more than once automatically using the iteration count Using an iteration count of zero will execute the BIST until the break Ctrl C command is pressed for example 10 T14 Execute T14 ten times 0 T5 Execute T5 forever The iteration counter can also be used to execute a sequence of tests more than once for example 5 T14 T15 T16 Execute T14 T15...

Page 92: ...lays a list of boards in the system their status and the active default slot number Boards are identified by logical slot number Only Concurrent Technologies boards configured for VSA mode will be identified by this command PRINT Short command PR Toggles the BIST printing flag When PRINT is off BIST diagnostic messages are not displayed during testing only the pass or fail and error code are displ...

Page 93: ... or a BIST time out is generated for a remote slot TEST p1 p2 Short command T test number in the range 0 255 p1 p2 test parameters see individual BIST descriptions for details Starts test execution on the default slot the supplied parameters are passed to the BIST TESTMENU Short command TM Displays a list of available BISTs for the default slot together with their associated test number UTILHELP S...

Page 94: ...ecified memory address DD address length read a dword from the specified memory address DQ address length read a qword 64 bits from the specified memory address SB address data write a byte to the specified memory address SW address data write a word to the specified memory address SD address data write a dword to the specified memory address NOTE The I O and memory read and write functions only o...

Page 95: ...is set to the VSA position the BIOS will transfer control to the VSA firmware once it has completed chipset initialization cache and memory sizing The VSA firmware performs additional hardware initialization and some basic functional checks before switching to Protected Mode and entering its master or slave test handler These functional checks are described below 11 1 1 Check 16 CPU Alive Check To...

Page 96: ...um Value A feature of the test is that if the expected checksum value is set to a value of 0FFFFFFFFh 1 in decimal then the test will always pass but will report the actual checksum value to the test master This is useful for discovering the new checksum value of a modified range Note that if the checksum area is defined to cover the three words that control the test it will not be possible to cal...

Page 97: ...used by VSA to communicate between boards Error codes 0300h Test failed 11 2 6 Test 9 8254 PIT Test This BIST checks the PC compatible Programmable Interval Timers within the CSB5 To test the secondary PIT PIT2 see Test 40 Each timer in turn is initialized with a start count value then monitored to make sure that it counts successfully Error codes 0401h Timer 0 failed to count 0402h Timer 1 failed...

Page 98: ...e memory under test is initialized to 00000000 Then two marches are made through memory with patterns as follows pass 1 new FFFFFFFF old 00000000 pass 2 new 00000000 old FFFFFFFF During the march through the memory range for every 32 bit word location first the old pattern is verified then the new pattern is written and verified To reduce execution time this BIST runs from DRAM however the area of...

Page 99: ...he slave test handler e g during soak testing the test range is limited to 64 Mbytes however each time the BIST is executed it tests a different block Therefore over the duration of a soak test run the whole of memory will be tested a number of times but the overall test coverage will be improved for large memory capacity boards When the test is executed from the master test handler the test range...

Page 100: ...r occurred 11 2 15 Test 27 Local RAM Execution Test This BIST executes code from RAM in the selected test region The range of memory to be tested depends upon the test handler from which the BIST was invoked When the test is executed from the slave test handler e g during soak testing the test range is limited to 64 Mbytes however each time the BIST is executed it tests a different block Therefore...

Page 101: ... compare after write 11 2 18 Test 30 SCC External Loopback This BIST performs an External Loopback Test on the serial channel of the board Channel A should be looped back externally by connecting TxDA to RxDB RxDA to TxDB DSR and RI to DTR RTS to CTS and CD and TxCA TxCB RxCA and RxCB together The test sequence is identical to the Internal Loopback Test described above followed by a test in which ...

Page 102: ... the VME bus The test requires another board in the VME rack to test with The test works by configuring a Universe PCI slave image for VME bus access writing known Byte Word and Double word values to the slave VME board then enabling Byte Swapping in the control register Quad word values are written and read by 64 bit DMA transfer The data is read back and compared with expected values any discrep...

Page 103: ...nterrupt This sub test checks the operation of the VME Bus Error Detection facility The Universe is configured for the duration of the sub test to map free PCI memory to a non existent 64k block of VME memory starting at address 0E0000000h The sub test reads the VME memory and checks that the VME bus error generates an interrupt within 1 ms 11 2 23 3 Sub Test 3 VME Bus Error Address Capture This s...

Page 104: ... of the watchdog to generate an NMI when its time out expires 11 2 24 2 Sub Test 2 Watchdog Reset Test This sub test checks the ability of the watchdog to reset the board when the time out counter expires The test first checks that the watchdog can operate without generating a reset or NMI while being patted NOTE The successful completion of this BIST will result in the board being reset Error cod...

Page 105: ...he frequencies of the PIT The LDT s holding register is set to an appropriate value and the LDT is started The sub test checks that a roll over is generated causing an interrupt within an appropriate time This sub test is then repeated for all the frequencies of the PIT Error codes 0400h sub test does not exist 0410h LDT failed standard test 0411h PIT failed standard test when programmed frequency...

Page 106: ...ataFlash The original contents of the device are preserved and restored on successful completion The sub tests options are 0 Test all sectors in all StrataFlash devices Default test 1 Test one sector Followed by Device from 0 Sector in device from 0 Error codes 0401h error during sector erase 0402h error during sector write 0403h error during sector verify 0404h sector locked error 0405h unknown S...

Page 107: ...ations across the NVRAM The original contents of the memory is saved and restored on successful completion of the sub test A marching I 0 pattern is used during the test 11 2 29 2 Sub test 2 NVRAM Data retention Pattern Setup This sub test performs a destructive write then read test on the NVRAM The test uses the absolute NVRAM offset as a pattern The pattern remains in memory on successful comple...

Page 108: ...d check on the controllers internal registers The sectors per track sector number and low cylinder count registers are tested 11 2 30 2 Controller Diagnostics Test This sub test invokes the IDE controller s internal diagnostic check If the check fails the diagnostic error code is displayed 11 2 30 3 Identify Disk Drive This sub test uses the Identify Drive command to interrogate the controller on ...

Page 109: ...ddress Lines l Chip Select Lines l Data Lines l DMA Channels Error codes The error codes for this BIST are returned as a range of error codes the least significant digital representing the point at which it failed in the test sequence For example 0436h identifies that DMA failed during the transfer of byte 6 040yh Register Test Failed on Byte y 041yh Chip Select Failed on Byte y 042yh Data Test Fa...

Page 110: ... 2 port Error codes 0401 Time out trying to flush keyboard controller buffer 0402 Keyboard controller did not read auxiliary enable command 0403 Keyboard controller did not read mode command 0404 Keyboard controller did not read mode command data 0405 No echo from auxiliary port 0406 Wrong echo from auxiliary port 0407 PS 2 mouse did not find 0408 PS 2 mouse report error after reset 0409 No identi...

Page 111: ...read keyboard enable command 0403h Keyboard controller did not read mode command 0404h Keyboard controller did not read mode command data 0405h Self test command not read 0406h Time out waiting for self test result 0407h Self test fail 0408h Keyboard controller not ready after self test 0409h Interface test command not read 040Ah Time out waiting for interface test result 040Bh Interface test fail...

Page 112: ...tents of NVRAM 3 Display contents of NVRAM 4 Non destructive read write test of NVRAM The RTC periodic interrupt is allowed to interrupt twice to test that the interrupt is acknowledged correctly The read write test checks each location of NVRAM excluding the RTC registers Each address is tested first with 0x55 then with 0xAA The contents of NVRAM is saved and restored around the test Error codes ...

Page 113: ...t performs a series of checks on the 82559ER internal functions a rolling bit tests on the chip s pointer register reset tests selective and software internal self tests single and multiple command execution and interrupt generation 11 2 35 3 Sub Test 2 Internal Loopback This sub test verifies the transfer of Ethernet frames using the internal loopback path of the controller 11 2 35 4 Sub Test 3 E...

Page 114: ...r the CPU sensor will always read 0 C The CPU sensor is not connected to Vcc Should this error occur both the ambient and CPU sensors will always read 127 C 11 2 36 2 Temperature Readout This sub test will perform a basic functionality test display the current temperature readings and finally check that the CPU has not breached the 95 C alarm Should this alarm be triggered or basic diagnostics fai...

Page 115: ...l possible options are listed below Value Update Frequency Hz 0 0 0625 1 0 125 2 0 25 3 0 5 4 1 5 2 6 4 7 8 Alarms will only trigger when an update occurs Should there be a temperature spike between readings it will not trigger an alarm If this is a problem raise the update frequency to 8Hz VP 110 01x 11 21 VSA Mode Diagnostics ...

Page 116: ...tivated since the last check There are four alarms which may be triggered Every pair of readings taken by the Maxim 1617 Thermal Sensor are compared against the thresholds and will flag any relevant alarms Error codes 040Ah Read or write request to an invalid device 040Bh Bad data type requested 040Ch Multiple termination conditions exist 040Dh Invalid command line parameter 0411h Process was KILL...

Page 117: ...dware The BIST comprises a number of sub tests of which only the Floppy Controller test is run by default The BIST operates on drive A by default however drive B can be specified by a BIST parameter 11 2 39 1 Controller Access Test This sub test checks access to the floppy disk controller hardware No disk drive is required for this test 11 2 39 2 Diskette Access Test This sub test checks access to...

Page 118: ... it should only be run in an interactive manner by a local or remote test master The parameters are start address of memory area default 0 data type 1 for byte 2 for word and 4 for dword default 1 length of RAM area in bytes default 1 constant value with which to fill the area default 0 This is not a true BIST but merely provides a utility function and so always returns a PASS status 11 2 42 Test ...

Page 119: ...ctly so it should only be run in an interactive manner by a local or remote test master The parameter is interconnect register number 16 bit value The result is displayed as a hexadecimal value This is not a true BIST but merely provides a utility function and so always returns a PASS status 11 2 45 Test 106 Interconnect Write Utility This BIST allows a local interconnect write to be performed on ...

Page 120: ...ration EPROM Caching should not be disabled When EPROM caching is disabled ROM based timing loops are disrupted which can cause BISTs to time out or fail 11 2 47 Test 120 PCI Configuration Utility This BIST will display for each device on the PCI bus the vendor identification number device identification number and the device revision number For example Bus Dev Func Vendor ID Device ID Revision 00...

Page 121: ...t should only be run in an interactive manner by a local or remote test master The parameters are Device number 0 to 31 default 0 Register Offset 0 to 255 default 0 Value to write Default 0 Data Type 1 Byte 2 Word or 4 Dword default 2 Length number of bytes words Dwords Bus Number 0 to 255 default 0 Function Number 0 to 7 default 0 Verify 0 no verify 1 verify by reading back default 0 11 2 50 Test...

Page 122: ...This page has been left intentionally blank 11 28 VP 110 01x VSA Mode Diagnostics ...

Page 123: ... EIDE Ultra ATA100 interface via P2 and on board mass storage option inter face Floppy disk interface via P2 supporting up to 1 Mbits s transfer rates and 2 floppy disk drives A USB interface via connector P2 Both 1 5 and 12 Mbits s interfaces sup ported Two single or one double width PMC sites supporting a 64 32 bit 66 33MHz PCI interface with 5V or 3 3V signaling Both 5V and 3 3V power rails are...

Page 124: ...elf discharge It is therefore recommended that the battery be removed during storage A 2 2 Humidity Operating 10 to 90 non condensing Storage 10 to 90 non condensing A 3 Dimensions Height 23 3cm Depth 16 0cm Width 2 0cm Weight 500g without Mass Storage Kit fitted A 4 Electrical Specification A 4 1 Power Supply Requirements VOLTAGE V PROCESSOR REGULATION CURRENT SPEED Typical 5 0V 1 2GHz 5 3 8 0A 5...

Page 125: ...cations VP 110 01x A 3 J9 J15 J16 J3 J6 S1 J21 J23 J11 J13 J14 J1 P2 P0 P1 J12 J24 J22 Figure A 1 Connector Layout Ethernet CH1 PMC Site 2 PMC Site 1 Ethernet CH0 COM1 External Reset Ground Figure A 2 Front Panel Connectors ...

Page 126: ...T GND 10 GND SYSCLK BG3IN SYSFAIL GAP 11 GND BG3OUT BERR GA0 12 GND DS1 BR0 SYSRESET GA1 13 DS0 BR1 LWORD 14 GND WRITE BR2 AM5 GA2 15 GND BR3 A23 16 GND DTACK AM0 A22 GA3 17 GND AM1 A21 18 GND AS AM2 A20 GA4 19 GND AM3 A19 20 GND IACK GND A18 21 IACKIN A17 22 GND IACKOUT A16 23 AM4 GND A15 24 GND A07 IRQ7 A14 25 A06 IRQ6 A13 26 GND A05 IRQ5 A12 27 A04 IRQ4 A11 28 GND A03 IRQ3 A10 29 A02 IRQ2 A09 3...

Page 127: ...I O 28 D16 PMC Slot 1 I O 27 IDED14 15 DIR PMC Slot 1 I O 30 D17 PMC Slot 1 I O 29 IDED1 16 GND PMC Slot 1 I O 32 D18 PMC Slot 1 I O 31 IDED15 17 STEP PMC Slot 1 I O 34 D19 PMC Slot 1 I O 33 IDED0 18 GND PMC Slot 1 I O 36 D20 PMC Slot 1 I O 35 IDEDRQ 19 WRDATA PMC Slot 1 I O 38 D21 PMC Slot 1 I O 37 IDEIOW 20 GND PMC Slot 1 I O 40 D22 PMC Slot 1 I O 39 IDEIOR 21 WE PMC Slot 1 I O 42 D23 PMC Slot 1...

Page 128: ... I O 8 I O 9 I O 10 6 GND I O 11 I O 12 I O 13 I O 14 I O 15 7 GND I O 16 I O 17 I O 18 I O 19 I O 20 8 GND I O 21 I O 22 I O 23 I O 24 I O 25 9 GND 10 GND 11 GND 12 GND I O 26 I O 27 I O 28 I O 29 I O 30 13 GND I O 31 I O 32 I O 33 I O 34 I O 35 14 GND I O 36 I O 37 I O 38 I O 39 I O 40 15 GND I O 41 I O 42 I O 43 I O 44 I O 45 16 GND I O 46 I O 47 I O 48 I O 49 I O 50 17 GND I O 51 I O 52 I O 53...

Page 129: ... No Signal Name 1 KBD VCC 5 MOUSE GND 2 KBD DATA 6 MOUSE CLOCK 3 KBD CLOCK 7 MOUSE DATA 4 KBD GND 8 MOUSE VCC Table A 4 Keyboard and Mouse Header LK1 Pin outs CAUTION The header is not polarized so care should be taken to ensure the cable socket is plugged in correctly The header pin out has been chosen to ensure damage will not occur to the keyboard or mouse if the cable is inadvertently connecte...

Page 130: ...oard Table A 5 Serial Port Cable Connections The standard PC AT serial port connector is a 9 way Male Sub miniature D type The correspondence between the VP 110 01x RJ45 serial connector pin out and the PC AT serial connector pin out is defined in the table below Signal Name RJ45 Pin PC AT Pin RTS Request To Send 1 7 DTR Data Terminal Ready 2 4 GND 3 5 TX Tx Data 4 3 RX Rx Data 5 2 CD Carrier Dete...

Page 131: ...the following pin out Pin No Signal Name 1 Transmit 2 Transmit 3 Receive 4 Not used 5 Not used 6 Receive 7 Not used 8 Not used Table A 7 Ethernet RJ 45 Connector Pin outs NOTE Ethernet channel 0 connects to J16 Specifications VP 110 01x A 9 1 2 3 4 5 6 7 8 Figure A 5 Ethernet RJ 45 Connector Front View ...

Page 132: ...1 11 SDD3 12 SDD12 13 SDD2 14 SDD13 15 SDD1 16 SDD14 17 SDD0 18 SDD15 19 GND 20 3 3 21 SDREQ 22 GND 23 SDIOW 24 GND 25 SDIOR 26 GND 27 SIORDY 28 NC 29 SDDACK 30 GND 31 INT15 32 NC 33 SDA1 34 PDIAG 35 SDA0 36 SDA2 37 SDCS1 38 SDCS3 39 ACTIVITY 40 GND 41 5V 42 5V MOTOR 43 GND 44 NC Table A 8 On Board Mass Storage Option Interface Pin outs Specifications A 10 VP 110 01x ...

Page 133: ... AD 25 24 GND 25 GND 26 C BE 3 27 AD 22 28 AD 21 29 AD 19 30 5V 31 V I O 32 AD 17 33 FRAME 34 GND 35 GND 36 IRDY 37 DEVSEL 38 5V 39 GND 40 LOCK 41 SDONE 42 SBO 43 PAR 44 GND 45 V I O 46 AD 15 47 AD 12 48 AD 11 49 AD 09 50 5V 51 GND 52 C BE 0 53 AD 06 54 AD 05 55 AD 04 56 GND 57 V I O 58 AD 03 59 AD 02 60 AD 01 61 AD 00 62 5V 63 GND 64 REQ64 V I O can be 5V or 3 3 V depending on board configuration...

Page 134: ...42 SERR 43 C BE 1 44 GND 45 AD 14 46 AD 13 47 M66EN 48 AD 10 49 AD 08 50 3 3V 51 AD 07 52 REQ B 53 3 3V 54 GNT B 55 PMC RSVD 56 GND 57 PMC RSVD 58 PMC1_EREADY 59 GND 60 61 ACK64 62 3 3V 63 GND 64 3 3V denotes active low pulled high via 1KOhm resistor pulled high via 10KOhm resistor Table A 10 PMC J12 Connector Pin outs NOTE IDSEL B REQ B and GNT B are provided for use by dual function PMC modules ...

Page 135: ...2 AD 56 23 AD 55 24 AD 54 25 AD 53 26 GND 27 GND 28 AD 52 29 AD 51 30 AD 50 31 AD 49 32 GND 33 GND 34 AD 48 35 AD 47 36 AD 46 37 AD 45 38 GND 39 V I O 40 AD 44 41 AD 43 42 AD 42 43 AD 41 44 GND 45 GND 46 AD 40 47 AD 39 48 AD 38 49 AD 37 50 GND 51 GND 52 AD 36 53 AD 35 54 AD 34 55 AD 33 56 GND 57 V I O 58 AD 32 59 60 61 62 GND 63 GND 64 Table A 11 PMC J13 Connector Pin outs Specifications VP 110 01...

Page 136: ...I O 25 26 I O 26 27 I O 27 28 I O 28 29 I O 29 30 I O 30 31 I O 31 32 I O 32 33 I O 33 34 I O 34 35 I O 35 36 I O 36 37 I O 37 38 I O 38 39 I O 39 40 I O 40 41 I O 41 42 I O 42 43 I O 43 44 I O 44 45 I O 45 46 I O 46 47 I O 47 48 I O 48 49 I O 49 50 I O 50 51 I O 51 52 I O 52 53 I O 53 54 I O 54 55 I O 55 56 I O 56 57 I O 57 58 I O 58 59 I O 59 60 I O 60 61 I O 61 62 I O 62 63 I O 63 64 I O 64 Tab...

Page 137: ...23 AD 25 24 GND 25 GND 26 C BE 3 27 AD 22 28 AD 21 29 AD 19 30 5V 31 V I O 32 AD 17 33 FRAME 34 GND 35 GND 36 IRDY 37 DEVSEL 38 5V 39 GND 40 LOCK 41 SDONE 42 SBO 43 PAR 44 GND 45 V I O 46 AD 15 47 AD 12 48 AD 11 49 AD 09 50 5V 51 GND 52 C BE 0 53 AD 06 54 AD 05 55 AD 04 56 GND 57 V I O 58 AD 03 59 AD 02 60 AD 01 61 AD 00 62 5V 63 GND 64 REQ64 V I O can be 5V or 3 3 V depending on board configurati...

Page 138: ...42 SERR 43 C BE 1 44 GND 45 AD 14 46 AD 13 47 M66EN 48 AD 10 49 AD 08 50 3 3V 51 AD 07 52 REQ D 53 3 3V 54 GNT D 55 PMC RSVD 56 GND 57 PMC RSVD 58 PMC2_EREADY 59 GND 60 61 ACK64 62 3 3V 63 GND 64 3 3V denotes active low pulled high via 1KOhm resistor pulled high via 10KOhm resistor Table A 14 PMC J22 Connector Pin outs NOTE IDSEL D REQ D and GNT D are provided for use by dual function PMC modules ...

Page 139: ...2 AD 56 23 AD 55 24 AD 54 25 AD 53 26 GND 27 GND 28 AD 52 29 AD 51 30 AD 50 31 AD 49 32 GND 33 GND 34 AD 48 35 AD 47 36 AD 46 37 AD 45 38 GND 39 V I O 40 AD 44 41 AD 43 42 AD 42 43 AD 41 44 GND 45 GND 46 AD 40 47 AD 39 48 AD 38 49 AD 37 50 GND 51 GND 52 AD 36 53 AD 35 54 AD 34 55 AD 33 56 GND 57 V I O 58 AD 32 59 60 61 62 GND 63 GND 64 Table A 15 PMC J23 Connector Pin outs VP 110 01x A 17 Specific...

Page 140: ...I O 25 26 I O 26 27 I O 27 28 I O 28 29 I O 29 30 I O 30 31 I O 31 32 I O 32 33 I O 33 34 I O 34 35 I O 35 36 I O 36 37 I O 37 38 I O 38 39 I O 39 40 I O 40 41 I O 41 42 I O 42 43 I O 43 44 I O 44 45 I O 45 46 I O 46 47 I O 47 48 I O 48 49 I O 49 50 I O 50 51 I O 51 52 I O 52 53 I O 53 54 I O 54 55 I O 55 56 I O 56 57 I O 57 58 I O 58 59 I O 59 60 I O 60 61 I O 61 62 I O 62 63 I O 63 64 I O 64 Tab...

Page 141: ...ctor with the following pin out Pin No Signal Name 1 GND 2 CPU Reset 3 GND 4 Debug Reset 5 GND 6 CPU TCK 7 CPU TDI 8 CPU TMS 9 CPU TDO 10 Pull Up 11 CPU TRST 12 NC 13 NC 14 GND 15 CPU REQ 16 GND 17 CPU RDY 18 GND 19 NC 20 GND 21 Pull Up 22 GND 23 NC 24 GND 25 Pull Up 26 NC 27 NC 28 GND 29 Pull Up 30 GND Table A 17 30 way Debug Connector Pin outs VP 110 01x A 19 Specifications ...

Page 142: ... 1 GND 2 Not Connected 3 Port 80 Select 4 Not Connected 5 D3 6 D7 7 D2 8 D6 9 D1 10 D5 11 D0 12 D4 13 5 Volts 14 GND Table A 18 Port 80 Connector Pin outs A 20 VP 110 01x Specifications 1 3 5 2 4 6 7 8 9 10 11 12 13 14 Figure A 6 Port 80 Connector ...

Page 143: ...r I O of the VP 110 01x An overview of each breakout module is given with a reference to a pin out table for each of the connectors identified B 2 Breakout Modules List The following breakout modules are suitable for use with the VP 110 01x Sales Part No Board number as marked on PCB AD VP2 004 10 720 6123 00 AD VP2 004 20 720 6123 01 AD VP2 005 00 720 6119 00 Table B 1 Breakout Modules List VP 11...

Page 144: ...idth behind the backplane B 3 1 Layout Figure B 1 shows the position of connectors and headers The AD VP2 004 10 requires a minimum of 75mm depth behind the VME backplane This measurement is taken from the mating face of the rear P2 connector B 3 2 Pin out Tables PMC Site 1 I O 1 32 Table B 5 PMC Site 1 I O 33 64 Table B 6 PMC Site 1 I O 1 64 Table B 7 B 2 VP 110 01x Breakout Modules P1 P5 PMC Sit...

Page 145: ...es one slot width behind the backplane B 4 1 Layout Figure B 2 shows the position of connectors and headers The AD VP2 004 20 requires a minimum of 75mm depth behind the VME backplane This measurement is taken from the mating face of the rear P2 connector B 4 2 Pin out Tables Floppy Table B 2 EIDE Table B 3 USB Table B 4 PMC Site 1 I O 1 32 Table B 5 PMC Site 1 I O 33 64 Table B 6 PMC Site 1 I O 1...

Page 146: ... 005 00 requires a minimum of 70mm depth behind the VME backplane This measurement is taken from the mating face of the rear P2 connector B 5 2 Pin out Tables Floppy Table B 2 EIDE Table B 3 USB Table B 4 PMC Site 1 I O 1 32 Table B 5 PMC Site 1 I O 33 64 Table B 6 PMC Site 2 I O 1 32 Table B 5 PMC Site 2 I O 33 64 Table B 6 B 4 VP 110 01x Breakout Modules PMC Site 1 I O 1 32 PMC Site 2 I O 1 32 U...

Page 147: ...D 20 STEP 21 GND 22 WRDATA 23 GND 24 WE 25 GND 26 TRK0 27 GND 28 WP 29 GND 30 RDDATA 31 GND 32 HDSEL 33 GND 34 DSKCHG Table B 2 Floppy 34 way IDC Header Pin No Signal Name Pin No Signal Name 1 IDERST 2 GND 3 IDEDD7 4 IDEDD8 5 IDEDD6 6 IDEDD9 7 IDEDD5 8 IDEDD10 9 IDEDD4 10 IDEDD11 11 IDEDD3 12 IDEDD12 13 IDEDD2 14 IDEDD13 15 IDEDD1 16 IDEDD14 17 IDEDD0 18 IDEDD15 19 GND 20 NC 21 IDEDRQ 22 GND 23 ID...

Page 148: ...6 27 I O 27 28 I O 28 29 I O 29 30 I O 30 31 I O 31 32 I O 32 33 GND 34 GND Table B 5 PMC I O 1 32 IDC Header Pin outs Pin No Signal Name Pin No Signal Name 1 I O 33 2 I O 34 3 I O 35 4 I O 36 5 I O 37 6 I O 38 7 I O 39 8 I O 40 9 I O 41 10 I O 42 11 I O 43 12 I O 44 13 I O 45 14 I O 46 15 I O 47 16 I O 48 17 I O 49 18 I O 50 19 I O 51 20 I O 52 21 I O 53 22 I O 54 23 I O 55 24 I O 56 25 I O 57 26...

Page 149: ...14 I O 27 48 I O 28 15 I O 29 49 I O 30 16 I O 31 50 I O 32 17 I O 33 51 I O 34 18 NC 52 NC 19 NC 53 NC 20 I O 35 54 I O 36 21 I O 37 55 I O 38 22 I O 39 56 I O 40 23 I O 41 57 I O 42 24 I O 43 58 I O 44 25 I O 45 59 I O 46 26 I O 47 60 I O 48 27 I O 49 61 I O 50 28 I O 51 62 I O 52 29 I O 53 63 I O 54 30 I O 55 64 I O 56 31 I O 57 65 I O 58 32 I O 59 66 I O 60 33 I O 61 67 I O 62 34 I O 63 68 I O...

Page 150: ...This page has been left intentionally blank B 8 VP 110 01x Breakout Modules ...

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